[PDF] ILP Based Approaches for Optimizing Early Decompute in Two Level Adiabatic Logic Circuits Y USHIODA, M KANEKO - IEICE Transactions on Fundamentals of Electronics …, 2023 Adiabatic logic circuits are regarded as one of the most attractive solutions for low- power circuit design. This study is dedicated to optimizing the design of the Two- Level Adiabatic Logic (2LAL) circuit, which boasts a relatively simple structure and superior low-power performance among many asymptotically adiabatic or quasi- adiabatic logic families, but suffers from a large number of timing buffers for “decompute”. Our focus is on the “early decompute” technique for fully pipelined …