@Tim Edwards & @Mitch Bailey: Hi Tim and Mitch, I'm running into issues with Dnwell in Magic where it is complaining about the the overlapping of the nwell guard ring and dnwell. Klayout DRC is clean but Magic's not. Magic version is 8.3.389, while klayout is 0.27.10. The layout is the final target form of the 4bit width version. I'm assuming this is due to magic is not up to date that's causing this?

@JC: Yes. Version 8.3.426 (pushed last Sunday) fixed this error. I confirmed on an older version that the error was there, then updated magic and the error went away.

I understand. May I have the recommended recipe to update magic and also the other tools as well? I don't think I spot the method to update magic in opencircuitdesign.com...

@JC I think you have them reversed. nwell extension beyond dnwell (outside overlap) is 0.4um and the internal overlap is 1.03um.

gotcha, so nwell goes into dnwell 1.03um and 0.4um is dangling on the outside

When you say

extract all

can’t complete, what do you mean? (

extract unique

is a directive that sets the option to re-label duplicate pins that are not connected. It does not run extraction.)

Looks like the errors are :

feedback add "Illegal overlap between pwell and nwell (types do not connect)" medium

I thought ext2spice will not work when there are errors. My thoughts were if I don't have the extract complete message, the .ext file will not be generated.

Do you have

pwell

in the layout?

pwell

is not used and is unneeded.

There shouldn't be pwells in there... I did the layout in klayout then open gds with magic. Inspecting the layout in magic, it looks like it's treating the nsdm(93/44) and psdm tap I drew into pwell. It did not have issue on the 4bit width version which is smaller.

ok. I assume that you’ve used other layout editors and extraction tools. magic extracts strictly hierarchically. Meaning each level must have valid data. In this case, each cell with deep nwell must be enclosed by an nwell ring. As you can see from the screen shot, the top and bottom nwell guard rings have been removed. magic does not look at the overall hierarchy when extracting subcells. One thing you might try is removing the deep nwell and nwell guardring from bitfour and just covering the whole bitsixtyfour with deep nwell surrounded by nwell. Incidentally, magic’s calculation for pwell is

layer pwell TAP,DIFF
 and-not NWELL,nwelcheck
 grow 130
 or SUBTXT,SUBPIN
 grow 420
 shrink 420
 labels SUBPIN port
 labels SUBTXT text

so tap and diff outside of nwell, sized by +0.13um and then sized by +0.42/-0.42 to merge adjacent areas. Is there any area where this calculation overlaps nwell?

Ah, I see where I went wrong with making the 64bit width layout. I was too hasty. For the nwell guard ring I have it set within the nwell with 0.63um from tap to nwell edge. For the nmos guard rings, I think the only place closest to nwell are the nmos transistors in image 3. Is the nsdm and psdm(guard ring) 0.13um spacing not enough?

I’m not sure. Is that where the errors are showing?

Taking out the 4bit width nwell guard ring and then making the big 64bit width nwell guard ring took care of the error.