Hi all in caravel's dv there are other testbenches such as gpio, gpio_mgmt(caravel/verilog/dv/caravel/mgmt_soc/gpio) - they are failing in when i try to do a simulation? it ends with error : Monitor: Timeout, Test GPIO (RTL) Failed any idea to get the fix for it to pass? or why is it failing? any inputs would be helpful thank you!

You're able to get those testbenches to run? I use them, but the openlane team has moved on to the "cocotb" system. "Monitor: Timeout" is a pretty generic error description. As long as it can pass syntax checks and get to simulation, pretty much anything that goes wrong will just cause the testbench to time out. You really have to look at the waveforms in gtkwave to figure out if the processor was running and if code was being executed.