@Marwan Abbas i still get this error. I changed my single file name to user_project_wrapper

@samarth jain You need to change the name of the top cell in the

user_project_wrapper.gds

file to

user_project_wrapper

. Digital designs (

user_project_wrapper

) also require a gate level

verilog/gl/user_project_wrapper.v

file.

but my digital design I routed using innovus and manually put it in design,did lvs and drc using cadence? what does a gate level

verilog/gl/user_project_wrapper.v

?

Innovous should have produced a gate level verilog netlist. Here’s a sample header from mpw-4 slot-005.

/*
###############################################################
#  Generated by:      Cadence Innovus 20.10-p004_1
#  OS:                Linux x86_64(Host ID merl-HP-Z840)
#  Generated on:      Thu Dec 30 02:09:58 2021
#  Design:            user_proj_example
#  Command:           eval_legacy {savenetlist -excludeLeafCell -includePowerGround -flat -exportTopPGNets user_proj_example_power.v}
###############################################################
*/
// Generated by Cadence Genus(TM) Synthesis Solution 20.11-s111_1
// Generated on: Dec 29 2021 11:09:14 PKT (Dec 29 2021 06:09:14 UTC)
// Verification Directory fv/user_proj_example

sure but why would it give below error due to digital?

The consistency check is probably due to the top gds name not being

user_project_wrapper

or missing gate level verilog. The XOR check means that the something has been changed in the surrounding power ring. There’s a region around the

user_project_wrapper

that must match the golden version.

@Tim Edwards @Mitch Bailey @mehdi ok but I am bit confused.My A part is analog devices made in cadence, b is innovus routed. We finally integrated all design in cadence and routed LA pins for debug and other pins all routed manually. then what should the

verilog/gl/user_project_wrapper.v

contain?

The top level

verilog/gl/user_project_wrapper.v

will just be the top level connectivity. You can probably create it manually without too much effort.

what is the function of this wrapper? as I have manually connected LA pins and the la pins are unlike GPIO analog pin. They don't have any mode for pull up or pull downs etc as we defined in user_define.v file. Also I passed the error and submitted the design. there was a small DRC error with a LA pin and wire from user design.

The tapeout job places the

user_project_wrapper

into the caravel framework. The consistency check verifies that all the interface pins and only the interface pins are present. The XOR check verifies that when the

user_project_wrapper

is placed, there will be no DRC/LVS errors with the caravel framework. The LA pin positions are fixed in caravel and the XOR check verifies that they have not been moved. The tapeout job does not do routing to the

user_projec_wrapper

. Everything is pre-routed to to fixed pin locations.