Hi all, regarding digital synthesis, I was using the following script but was not sure regarding max_load,max input delay ,max output delay values. I am getting the following violations. My design is a simple TDC based 256 parallel counters with communication to wishbone. Also do you know values I can use for max transition time ,max fanout and max capacitance?I am using synopsys design compiler https://open-source-silicon.slack.com/files/U053UFMPKDW/F05NYAVB6G0/sv_comp.tcl @Mitch Bailey