I'm trying to run Verilog-A using ngspice. I created a .va file as shown in the image below and compiled it into OSDI format using openvaf. Then, I created a .sp file as shown in the image below and tried to run it, but I encountered the following error. I would appreciate it if you could let me know what might be the issue. Thank you in advance for your help

I need to figure out how to use the OSDI feature myself, so I'll take a look at it. Won't be until tomorrow, though, so hopefully there's someone else who can help you before then (there was a bit of discussion about getting the OSDI models to run in the #reram channel a while back; you might want to check that).

Basically you have forgotten .Model in your test.sp : test.va : ``include "discipline.h"`

module resistor_va (p,n);

parameter real r=5;

inout p,n;

electrical p,n;

analog

V(p,n) <+ I(p,n) *r;

endmodule

test.sp :

*SPICE circuit

.Model resistor_model resistor_va ;

VDD v2 0 DC 5V

.subckt res p n

nres p n resistor_model

.ends

x1 v2 v1 res

x2 v1 0 res

.tran 0.01m 6m

.save v(v1)

.control

pre_osdi ./test.osdi

run

.endc

more examples : https://openvaf.semimod.de/docs/getting-started/examples/

@Michael Strothjohann: Thank you for the example netlist!