Hi all i wanted to check if iverilog takes in .sdf file format? if not what is the right way to see the actual delay in verilog simulation {or just use #? }

@Leo Moser is actively working on development of iverilog to allow delay annotation from SDF files. Meanwhile, you can try the "cvc" simulator (see http://www.tachyon-da.com/what-is-cvc/), which does support it.

Thanks a lot @Tim Edwards

Icarus Verilog already has support for the IOPATH delays needed for SKY130. I am currently working on implementing support for the SDF INTERCONNECT feature, here: https://github.com/steveicarus/iverilog/pull/973 It is currently very WIP, but I'd like to get it into a usable state by mid-September. Please note that iverilog does not currently support timing checks either, but that is something I want to look at as well.

Thank you @Leo Moser

Hi, I hope you are doing well and that this new year will be full of health, happiness and success for all of us. Hi @Leo Moser, I'm following your motivation on this very challenging task for almost a year. Personally, I think it will be extremely helpful for all the community, since sdf support is very important for verifying the correct behavior of the final chip design. If possible, I wanted to know the current status of the project, and if you think it will be something achievable soon. Thank you very much in advance! Best Regards, Rodrigo Iga

Hello @Rodrigo Iga, I hope you have a great year too! You can find my final project report for GSoC here: https://mole99.uber.space/2023/GSoC_Final/GSoC23%20%E2%80%94%20Final%20Project%20Report.html I agree that SDF support is very important for the chip design community, but sadly it's still lacking. I currently have a PR open for a first timing check in Icarus Verilog that already works on vvp's side, but I still need to do the plumbing at ivl to emit the correct code. This turned out to be more difficult than expected. https://github.com/steveicarus/iverilog/pull/999 Unfortunately, I haven't found much time after GSoC to continue my work on this. I hope to eventually complete this PR and maybe also add other timing checks. But with me working on it alone, I am afraid full spec compliant SDF support won't be anytime soon... Br, Leo

Hi @Leo Moser, first of all I wanted to thank you for your response, and of course for the very valuable job you have done with iVerilog, which is a great contribution for the open-source community. I have read all the final report information, and let me say that you have done an great job!! Even the week reports were great, because they transmit all the effort, some interesting details and the evolution of the done work. If I understood well, the SDF support (INTERCONNECT + IOPATH) is functional in the current version, only if enabling both, the "-gspecify" and the "-ginterconnect" options (I will upgrade to the current version).

Thanks @Rodrigo Iga, appreciate it 😃️ Exactly, you need to enable both options. This is the respository where I tested some OpenLane designs: https://github.com/mole99/interconnect-tests In the Makefile you can see how iverilog and vvp needs to be called. I too hope I can continue my work on it (with enough time), and that others may pick up on it 👍️

Thank you very much @Leo Moser . I hope it too, since this work is extremely important for the Open-Source community. Thank you again for your precious work.