I have made the VDD and GND rails however its saying VDD is has no matching pins. Does circuit 1 belong to the top verilog while circuit belong to the gds/lef generated from magic? What is the step to get VDD on magic's(circuit 2?) side as

Net: lane0/VDD

? Another thing is I have to update the macro_placement.cfg to

155 150 N

instead of

150 150 N

to avoid step 24 (Detailed Routing) violation. Why is this a thing? I have included the .log file for that. Thread in Slack Conversation