@donn @Kareem Farid Is there a reason to quit on "Resizing cell port" warnings during synthesis that I am not aware of? Generally, the tool should be able to remove unused wires before generating the netlist

Implicit width conversions are more often than not mistakes and their behavior may be undesirable. They are very easy to workaround: if your wire has a larger width than the port, use an index, for example, and if your wire has a lower width than the port, explicitly concatenate it to 1s or 0s if it's an input or declare a wire called "unused" and concatenate it as your output. IMO Verilog is not nearly strict enough as a language about these things. This should have never been allowed.

Okay, though Yosys lists it as a warning, I was assuming this should not be a fatal problem and Yosys would be able to handle it

Why leave something to implicit handling/truncation/padding when a simple mistake can cost you thousands of dollars?