I have very little knowledge about LVS mismatch errors. I'm getting LVS errors at final stage, during "make user_project_wrapper". Where to look in the reports? how to find out due to which macro the LVS mismatches are coming?

share the lvs log

28-user_project_wrapper.lef.lvs.log,28-user_project_wrapper.lef.lvs.json,28-lvs.lef.log

The lvs results here are for the abstracted

user_project_wrapper

. Each block of

user_project_wrapper

is assumed to match. The problem is that the ports for the sram macro don’t match.

vssd1                                      |vssd1                                      
(no matching pin)                          |wmask0                                     
csb1                                       |(no matching pin)                          
clk1                                       |(no matching pin)                          
wmask0[0]                                  |(no matching pin)                          
---------------------------------------------------------------------------------------
Cell pin lists are equivalent.
Device classes sky130_sram_1kbyte_1rw1r_8x1024_8 and sky130_sram_1kbyte_1rw1r_8x1024_8 are equivalent.

Can you add connections for

csb1

and

clk1

and change

wmask0

to

wmask0[0]

in the verilog sram instances? There may be a fixed version of

wmask0

in the dev repo of openram. See here and here.