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Hi, I am working on IHP technology integration wit...
# openroad
k
Hi, I am working on IHP technology integration with OpenRoad-flow-scripts and got some issues with detailed routing. The exact bug is the following 
[ERROR DRT-0307] Net _000_ of signal type SIGNAL cannot be connected to iterm _318_/Y with signal type POWER Error: detail_route.tcl, 59 DRT-0307 I
Here is my 
pdn.tcl
file content:
Copy code
####################################
# global connections
####################################
add_global_connection -net {VDD} -pin_pattern {^VDD$} -power
add_global_connection -net {VDD} -pin_pattern {^VDDPE$}
add_global_connection -net {VDD} -pin_pattern {^VDDCE$}
add_global_connection -net {VSS} -pin_pattern {^VSS$} -ground
add_global_connection -net {VSS} -pin_pattern {^VSSE$}
global_connect
####################################
# voltage domains
####################################
set_voltage_domain -name {CORE} -power {VDD} -ground {VSS}
#proc####################################
####################################
define_pdn_grid -name {grid} -voltage_domains {CORE}
add_pdn_ring -grid {grid} -layers {Metal5 TopMetal1} -widths {5.0} -spacings {2.0} -core_offsets {4.5} -connect_to_pads
add_pdn_stripe -grid {grid} -layer {Metal1}     -width {0.48}  -pitch {7.56} -offset {0}      -followpins -extend_to_core_ring
add_pdn_stripe -grid {grid} -layer {Metal5}     -width {2.200} -pitch {75.6} -offset {13.600}             -extend_to_core_ring
add_pdn_stripe -grid {grid} -layer {TopMetal1}  -width {1.800} -pitch {75.6} -offset {13.570}             -extend_to_core_ring
add_pdn_connect -grid {grid} -layers {Metal1 Metal5}
add_pdn_connect -grid {grid} -layers {Metal5 TopMetal1}
####################################
It generates the PDN network correctly. My 
MIN_ROUTING_LAYER ?= Metal1
and 
MAX_ROUTING_LAYER ?= Metal4
Any idea where the problem is ?
The exact connection is shown on the image, I have verified it is the gate level netlist and it seems to be ok. However still the router complains about signal type
a
looks like cell 318 declares Y output as power pin, you need to debug why
k
image.png
seems that it is declared as SIGNAL
My supposition is that there is something wrong with the Metal1. I followed the sky130hd scripts and one of the differences between SKY130 and IHP is that that met1 in SKY is horizontal and in IHP Metal1 is vertical. I do not know if it matters.
m
It is the iterm that has the issue not the net: 
iterm _318_/Y with signal type POWER
the question is what is the cell and in LEF what is the type for pin Y
k
Copy code
MACRO sg13g2_o21ai_1
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN sg13g2_o21ai_1 0 0 ;
  SIZE 2.4 BY 3.78 ;
  SYMMETRY X Y ;
  SITE CoreSite ;
  PIN B1
    DIRECTION INPUT ;
    USE SIGNAL ;
    ANTENNAMODEL OXIDE1 ;
      ANTENNAGATEAREA 0.279 LAYER Metal1 ;
    PORT
      LAYER Metal1 ;
        RECT 1.24 1.43 1.55 2.06 ;
    END
  END B1
  PIN VDD
    DIRECTION INOUT ;
    USE POWER ;
    PORT
      LAYER Metal1 ;
        RECT 0 3.56 2.4 4 ;
        RECT 1.77 2.64 1.93 4 ;
        RECT 0.18 2.3 0.34 4 ;
    END
  END VDD
  PIN Y
    DIRECTION OUTPUT ;
    USE POWER ;
    PORT
      LAYER Metal1 ;
        RECT 1.24 2.27 1.93 2.43 ;
        RECT 1.77 0.55 1.93 2.43 ;
        RECT 1.24 2.27 1.4 3.28 ;
    END
  END Y
  PIN VSS
    DIRECTION INOUT ;
    USE GROUND ;
    PORT
      LAYER Metal1 ;
        RECT 0 -0.22 2.4 0.22 ;
        RECT 0.71 -0.22 0.87 0.84 ;
    END
  END VSS
  PIN A1
    DIRECTION INPUT ;
    USE SIGNAL ;
    ANTENNAMODEL OXIDE1 ;
      ANTENNAGATEAREA 0.279 LAYER Metal1 ;
    PORT
      LAYER Metal1 ;
        RECT 0.11 1.42 0.46 2.09 ;
    END
  END A1
  PIN A2
    DIRECTION INPUT ;
    USE SIGNAL ;
    ANTENNAMODEL OXIDE1 ;
      ANTENNAGATEAREA 0.279 LAYER Metal1 ;
    PORT
      LAYER Metal1 ;
        RECT 0.67 1.43 1.02 2.46 ;
    END
  END A2
  OBS
    LAYER Metal1 ;
      RECT 0.13 1.06 1.45 1.22 ;
      RECT 1.24 0.55 1.4 1.22 ;
      RECT 0.18 0.55 0.34 1.22 ;
    LAYER Metal1 SPACING 0.18 ;
      RECT 0.64 1.02 1.59 1.25 ;
      RECT 1.05 0.4 1.59 1.25 ;
      RECT 0 1.02 1.59 1.24 ;
      RECT 0 0.4 0.53 1.24 ;
      RECT 2.11 0.4 2.4 3.38 ;
      RECT 0.52 2.64 1.06 3.38 ;
  END
END sg13g2_o21ai_1
seems that we have the response 
USE POWER
for the Y port is generating the issue
m
That seems to be the problem
k
let me check. I will let you know.
i
@Krzysztof Herman What is your objective of IHP integration with ORFS? Is it to enable analog/mixed signal type of designs in opentoad? Are you also planning to target to any of the SkyWater and GF public nodes ? Just curious... thanks
k
@Indira Iyer I work for IHP, we are enabling different open source tools and flows to work with IHP Open Source PDK and of course it will be released to the public domain.
i
Great to hear @Krzysztof Herman..thanks
k
The issue vas solved using 
USE SIGNAL;
in lef file. Thanks @Matt Liberty and @Arman Avetisyan. However there is another one:
Copy code
[ERROR DRT-0073] No access point for _442_/CLK.
[ERROR DRT-0073] No access point for _447_/CLK.
[INFO DRT-0076]   Complete 100 pins.
Error: detail_route.tcl, 59 DRT-0073
Any clue about that ?
a
post lef/def relevant sections of the cells in question
first guess: obstruction layer over the pin
k
The cell 442 and 447 is 
sg13g2_dfrbp_2
here goes its lef file
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MACRO sg13g2_dfrbp_2
  CLASS CORE ;
  ORIGIN 0 0 ;
  FOREIGN sg13g2_dfrbp_2 0 0 ;
  SIZE 14.4 BY 3.78 ;
  SYMMETRY X Y ;
  SITE CoreSite ;
  PIN RESET_B
    DIRECTION INPUT ;
    USE SIGNAL ;
    ANTENNAPARTIALCUTAREA 0.0361 LAYER Via1 ;
    ANTENNAMODEL OXIDE1 ;
      ANTENNAGATEAREA 0.1092 LAYER Metal1 ;
      ANTENNAGATEAREA 0.3276 LAYER Metal2 ;
      ANTENNAMAXAREACAR 1.142857 LAYER Metal2 ;
      ANTENNAMAXCUTCAR 0.330586 LAYER Via1 ;
    PORT
      LAYER Metal1 ;
        RECT 9.595 1.65 9.985 1.97 ;
        RECT 2.385 1.61 2.755 1.955 ;
        RECT 1.025 1.45 1.315 1.98 ;
      LAYER Metal2 ;
        RECT 9.64 1.58 9.93 1.965 ;
        RECT 1.075 1.58 9.93 1.78 ;
--
END sg13g2_dfrbp_2
here goes the LEF file section for this cell
sg13g2_dfrbp_2.txt
image.png
m
is it possible to share a test case?
k
@Matt Liberty yes, I can generate it however I solved it using sg13g2_dfrbp_1 cell so I suppose it is the matter of the cell itself. Are you still interested ?
detail_route_gcd_ihp-sg13g2_base_2023-08-09_15-59.zip
detail_route_gcd_ihp-sg13g2_base_2023-08-09_15-59.zip
m
So "No access point" is resolved?
m
@Matt Liberty Yes, in sg13g2_dfrbp_2 the clk-pin is not accessible - because it is covered by reset_b. This is a bug in IHPs stdcell - so has nothing to do with OR. (In sg13g2_dfrbp_1 the clk pin is not masked).
👍 1
k
@Matt Liberty @Michael Strothjohann yes indeed it is true. There are a few bugs in standard cells. We are working on that at IHP. I found also other issues with yosys. So I can run the flow only if I eliminate the 
-script $abc_script
from the following code.
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# Technology mapping for cells
# ABC supports multiple liberty files, but the hook from Yosys to ABC doesn't
if {[info exist ::env(ABC_CLOCK_PERIOD_IN_PS)]} {
  puts "\[FLOW\] Set ABC_CLOCK_PERIOD_IN_PS to: $::env(ABC_CLOCK_PERIOD_IN_PS)"
  abc -D [expr $::env(ABC_CLOCK_PERIOD_IN_PS)] \
      -script $abc_script \
      -liberty $::env(DONT_USE_SC_LIB) \
      -constr $::env(OBJECTS_DIR)/abc.constr
} else {
  puts "\[WARN\]\[FLOW\] No clock period constraints detected in design"
  abc -liberty $::env(DONT_USE_SC_LIB) \
      -constr $::env(OBJECTS_DIR)/abc.constr
}
If no it stops here
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[FLOW] Set ABC_CLOCK_PERIOD_IN_PS to: 30400 ./objects/ihp-sg13g2/gcd/base/lib/sg13g2_stdcell_typ_1p20V_25C.lib
8. Executing ABC pass (technology mapping using ABC).
8.1. Extracting gate netlist of module `\gcd' to `<abc-temp-dir>/input.blif'..
8.1.1. Executing ABC.
ERROR: ABC: execution of command "/home/herman/asic/digital/OpenROAD-flow-scripts/tools/install/yosys/bin/yosys-abc -s -f /tmp/yosys-abc-AsNr6w/abc.script 2>&1" failed: return code 1.
Command exited with non-zero status 1
Elapsed time: 0:00.91[h:]min:sec. CPU
The 
/tmp/yosys-abc-AsNr6w/abc.script
contains the following and seems to point to the valid directories:
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echo + read_blif /tmp/yosys-abc-AsNr6w/input.blif;
read_blif /tmp/yosys-abc-AsNr6w/input.blif;
echo + read_lib -w /home/herman/asic/digital/OpenROAD-flow-scripts/flow/./objects/ihp-sg13g2/gcd/base/lib/sg13g2_stdcell_typ_1p20V_25C.lib;
read_lib -w /home/herman/asic/digital/OpenROAD-flow-scripts/flow/./objects/ihp-sg13g2/gcd/base/lib/sg13g2_stdcell_typ_1p20V_25C.lib;
echo + source /home/herman/asic/digital/OpenROAD-flow-scripts/flow/./scripts/abc_speed.script;
source /home/herman/asic/digital/OpenROAD-flow-scripts/flow/./scripts/abc_speed.script;
echo + write_blif /tmp/yosys-abc-AsNr6w/output.blif;
write_blif /tmp/yosys-abc-AsNr6w/output.blif
m
@Krzysztof Herman A couple of weeks ago I had the same problem. Two optional 'workarounds': (a) delete line 72 in synth.tcl, so default script is used, or (b) delete the '- c's in the abc_area.script and abc_speed.script
k
@Michael Strothjohann thank you for the feedback. do you have any guess why it happens, it is a problem of yosys-abc or the issue sits inside *.lib file ?
m
I suspect the latter, because there are no problems with the libs from the other pdks.
Other groups (e.g. iguana - who develop a riscV with IHPs pdk) do not give an abc-script either, but use deault: see line 137 in https://github.com/pulp-platform/iguana/blob/main/target/ihp13/yosys/scripts/yosys_synthesis.tcl
🙌 1
m
what happens if you run abc directly? There isn't much of an error in the output you gave
m
If wire-loads are specified (as done in sg13g2_stdcell_typ_1p50V_25C.lib ) the -c option in abc_area and abc_speed toggels there use (default is no use of wire-loads, even if they are specified). So i guess there is a problem with wire-loads. After reformulating the wire-loads specification in sg13g2_stdcell_typ_1p50V_25C along the lines of sky130_fd_sc_hd__tt_025C_1v80.lib, synthesis works as expected ( even with the -c options in abc_area.script / abc_speed.script).
k
@Michael Strothjohann what do you mean reformulating ? If you look at booth wireload definitions the one from IHP provide more parameters and maybe this is an issue because they are not supported. I have checked the library with lc_shell of synopsys and it reports no error. Below I will post part of wire definitions in SKY and IHP PDK. sky130_fd_sc_hs__tt_025C_1v80.lib
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wire_load("Large") {                                                                                                                                                                           
       capacitance : 1.42e-05;                                                                                                                                                                      
       resistance : 0.0745;                                                                                                                                                                         
       slope : 8.3631;                                                                                                                                                                              
       fanout_length( 1, 23.2746);                                                                                                                                                                  
       fanout_length( 2, 32.1136);                                                                                                                                                                  
       fanout_length( 3, 48.4862);                                                                                                                                                                  
       fanout_length( 4, 64.0974);                                                                                                                                                                  
       fanout_length( 5, 86.2649);                                                                                                                                                                  
       fanout_length( 6, 84.2649);                                                                                                                                                                  
       }
sg13g2_stdcell_typ_1p20V_25C.lib
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wire_load_table ("0_5k") {                                                                                                                                                                        
     fanout_area (1, 0.36);                                                                                                                                                                          
     fanout_area (5, 1.8);                                                                                                                                                                           
     fanout_area (20, 7.22);                                                                                                                                                                         
     fanout_area (10000, 3607.6);                                                                                                                                                                    
     fanout_capacitance (1, 0.0001);                                                                                                                                                                 
     fanout_capacitance (5, 0.0009);                                                                                                                                                                 
     fanout_capacitance (20, 0.0032);                                                                                                                                                                
     fanout_capacitance (10000, 1.449);                                                                                                                                                              
     fanout_length (1, 7.89);                                                                                                                                                                        
     fanout_length (5, 47.32);                                                                                                                                                                       
     fanout_length (20, 169.4);                                                                                                                                                                      
     fanout_length (10000, 77204.7);                                                                                                                                                                 
     fanout_resistance (1, 0.0042);                                                                                                                                                                  
     fanout_resistance (5, 0.0254);                                                                                                                                                                  
     fanout_resistance (20, 0.0911);                                                                                                                                                                 
     fanout_resistance (10000, 41.52);                                                                                                                                                               
       }
@Matt Liberty when I run yosys-abc directly it outputs: 
Error: Cannot find wire load model "0_5k"
m
@Krzysztof Herman Here is a simplified minimal example for downgrading from wire_load_table() to wire_load() : 
wire_load ("1k") {
fanout_length (1, 9.93);
fanout_length (5, 59.59);
fanout_length (20, 215.6);
capacitance: 0.0002;
resistance: 0.0053;
slope: 10.9;
}
default_wire_load : "1k" ;
default_wire_load_mode : "top";
Note 1: The three fanout_lengths, capacitance and resistance are extracted from the original IHP-lib. Slop is also a rough estimate : slope ~ (215.6 - 9.93)/(20-1) ~ 10.9 Note 2: The 'create_wire_load' command generates the values you should use.
m
It would be easier to look at a small run than file snippets. Can you make a small test case to show the issue?
k
@Michael Strothjohann interesting approach. Seems that it would be the solution.
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