open-source-silicon.dev

```% get_nets -of_objects [get_pins mux1_I/cell0_I/Z]
_90596fdd3a560000_p_Net
% get_nets -of_objects [get_pins mux1_I/out]
_60586fdd3a560000_p_Net```
They're not the same net ... even though realistically they should be !
```% find_timing_path -from [all_inputs] -to  [get_pins mux1_I/cell0_I/Z]
_207070dd3a560000_p_PathEnd
% find_timing_path -from [all_inputs] -to [get_pins mux1_I/out]
%```
And as you see it finds timing path to the first one ... but not the second one ...

Its hard to say much without seeing the netlist.  Are you doing this in the sta binary or in openroad?

The net list is what I pasted above : <https://pastebin.com/tRejnKR1>  This is what I feed to the read_verilog.

I am using the standalone `sta` binary since that's what OpenLane2 seem to call for STA.

The two nets are different as they are at different levels in the hierarchy.  find_timing_paths doesn't stop on a hierarchical port (nor does report_checks)

Damn, I guess what I want to do is just not supported then :cry:
I'll have to find some workaround.