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Hi how re u? Im triying to port the SAR ADC form t...
# analog-design
j
Hi how re u? Im triying to port the SAR ADC form this pdf https://epub.jku.at/obvulihs/content/titleinfo/8694768 and i have a problem with de the preamplifier, the thesis uses SKY130, and im trying to do in gf180, so i tried to keep some ratios between the width form the mosfet. My question is: -How to improve the preamp´s gain? cascaded preamp? -why when a transistor gets polarized (i think its actually cutoff) it makes the another out´s capacitor gets discharged faster?
In the pictures is possible to see how the Vgs1 from "Out1" affects the discharge from the cap on "Out2" even when Vgs1 its cutoff (see that yellow curve never goes down, then the capcitor doenst discharge meaning the trnasistor doesnt conduct) i dont understand why this happens or how to fix it to amplify an small Vdiff when one of the inputs its grounded or have a very small value. I hope i was clear and thanks so much for reading and for ur answers! Have a nice day!
l
It works as intended. Zoom at it. What you have is two capacitors that are discharged at different speeds. The problem is that VCM is too low, so vout1 never completely discharges for your clock frequency. Try another VCM. Zoom at the clock period so we can see the signals better.
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You could also try a differential input signal. Both inputs should be sine waves with inverted polarities and same DC level.
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m
"The Design of a Comparator [The Analog Mind]" from Behzad Razavi provides a great explanation and design-method for the comparator. I can't see 
vdiff
(from plot) in your testbench, there is net 
Vdif
but this net should be a sinus which is raised by voltage 
Vcm
. Preasumably the inputs from your amp-symbol are Vin1 and Vin2, then Vin1=Vcm+sin(..)+1 while Vin2=Vcm, and therefore both ports will be affected by changing Vcm
✅ 1
j
Hi thank you so much, it was exactly how @Manuel M sayed!
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