Hi All ....Any idea regarding this issue while RTL...
# caravel
s
Hi All ....Any idea regarding this issue while RTL simulation in caravel integration
t
A bit hard to debug without knowing what
ring_counter_tb
is doing.
Ring_counter_tb is updated here please can check and if anything incorrect ?
verilog/dv/ring_counter/ring_counter_tb.v
t
@sangamanath : Testbench lines 33 and 34:
Copy code
assign mprj_io_0[3:0] = mprj_io[11:8];
	assign mprj_io[11]=mprj_io_1;
You are treating
mprj_io[11]
as both an output (line 33) and an input (line 34). Which is it? Your configuration in the C code has GPIO 8-11 all set as user project outputs, so what is the point of trying to set
mprj_io[11]
to value 1 in the simulation? Your output "MPRJ-IO state =" from the testbench is only printing out the state of the first 8 GPIOs, which doesn't include your project outputs. So you can't tell anything from that output. Chances are that if there is a single error here, it's that you have a conflict with two drivers on
mprj_io[11]
, so the value could be indeterminate, and if so, your testbench can never pass the checks for the value in
mprj_io[11:8]
.
s
in ring_counter.c
in ring_counter_tb.v
image.png
I made changes as above but i am not passing the simulation can you please suggest me what changes need to do in the above snaps?