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I tried /foss/examples/SKY130_SAR-ADC in Docker image(iic-osic-tools), but it failed in STEP 90, LVS error!! also I can see '[SUCCESS]: Flow complete.'. Is it failure or success? Can someone give me some advice?

<@U01889C8LQZ> Can you share `90-lvs-gds.log`?
You can check your `gds` directory to if a file was output, and if it was open that in `klayout` or `magic`.
If it did not create a gds file, you can set  `QUIT_ON_LVS_ERROR` to `0` in you configuration file and run again. See <https://openlane.readthedocs.io/en/latest/reference/configuration.html|here>.

It was an error at Step45 precisely.
Here are the gds(/foss/examples/SKY130_SAR-ADC1/openlane/adc_top/runs/ryos2/results/final/gds/adc_top.gds) and log file.

Ok, looks like there might be an unconnected net some where. (Or two separate nets that will be connected at a higher level).
```Circuit 1 contains 2327 devices, Circuit 2 contains 2327 devices.
Circuit 1 contains 2031 nets,    Circuit 2 contains 2030 nets. *** MISMATCH ***


Final result: 
Netlists do not match.
Logging to file "/foss/examples/SKY130_SAR-ADC1/openlane/adc_top/runs/ryos2/logs/signoff/45-adc_top.gds.lvs.log" disabled
LVS Done.```
Can you post `45-adc_top.gds.lvs.log`?

Hint: In klayout, use `File` -&gt; `Load Layer Properties` and select `$PDK_ROOT/$PDK/libs.tech/klayout/tech/$PDK.lyp` to show layer names/purposes.

attach a image after load layer properties and 45-adc_top.gds.lvs.log.

Looks like the `VDD` of the `cgen` instance is not connected to the top level `VDD`.
```Circuit 1: adc_top                         |Circuit 2: adc_top                         

---------------------------------------------------------------------------------------
Net: VDD                                   |Net: VDD                                   
  sky130_fd_sc_hd__inv_2/VPWR = 323        |  sky130_fd_sc_hd__inv_2/VPWR = 323        
...  
  sky130_fd_sc_hd__a21o_2/VPWR = 1         |  sky130_fd_sc_hd__a21o_2/VPWR = 1         
  sky130_fd_sc_hd__a21o_2/VPB = 1          |  sky130_fd_sc_hd__a21o_2/VPB = 1          
                                           |  adc_clkgen_with_edgedetect/VDD = 1       
                                           |                                           
Net: cgen/VDD                              |(no matching net)                          
  adc_clkgen_with_edgedetect/VDD = 1       |                                   ```

What is your `FP_PDN_MACRO_HOOKS` set to?

Trying to build this mixed-mode design in OL requires a few manual interactions during the flow, and is quite tricky. There should be no need to do it, just use the resulting .v/.lef/.gds when you want to use this macro in another design.

<@U017X0NM2E7>
Thank you for your advice. FP_PDN_MACRO_HOOKS is here.
```    "FP_PDN_MACRO_HOOKS": [
        "vcm  VDD VSS VDD VSS, ",
        "pmat VDD VSS VDD VSS, ",
        "nmat VDD VSS VDD VSS, ",
        "comp VDD VSS VDD VSS, ",
        "cgen VDD VSS VDD VSS, ",
        "obstruction1 VDD VSS VDD VSS, ",
        "obstruction2 VDD VSS VDD VSS "
    ]```
This is a sample in iic-osic-tools, which originated iic-jku/SKY130_SAR-ADC1.
I will check OpenROAD sources to understand what's happen. Thank you !!

<@U02UAUGSQ22> Thank you for your comment.
I just tried as a sample in iic-osic-tools. if you provide a simple sample of mixed signal project for OL, it helps us to understand analog design.

I tried also  ranan-usp/caravel_user_project_analog. It seems Success. I will discuss with <@U03S86AELQ6>.

Thank you !!