I try to create a Verilog digital component spice netlist to simulate with ngspice. I converted Verilog RTL to Verilog with a power pin using

vlog2Verilog

. Now with Yosys, I would like to convert this file to a spice file with

write_spice

. The steps that i follow are:

yosys

read_liberty -lib sky130_fd_sc_hd__tt_025C_1v80.lib

read_verilog counter.v

synth -top counter

When I run the last cmd I have this error :

3. Executing SYNTH pass.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Analyzing design hierarchy..
Top module:  \counter
ERROR: Module `sky130_fd_sc_hd__dfxtp_1' referenced in module `counter' in cell `_30_' does not have a port named 'VPWR'.

Yosys does synthesis, which means it never deals with power pins. You can use

vlog2Spice

from qflow (instead of/in addition to

vlog2Verilog

).

I need to install qflow or I can use openlane?

If you want those two programs

vlog2spice

and

vlog2verilog

, you would need to build qflow; they are standalone applications, though, so you wouldn't necessarily need to install qflow, just build it and grab the two programs. Qflow is a very lightweight application, and these are simple C code programs that should have no issues compiling.