Hello. I am trying caravel_user_project_analog as described in the following page, https://github.com/efabless/caravel_user_project_analog/blob/main/docs/source/index.rst but I get the following error in the dv test. Could you please tell me how to solve this problem?

hayato@md22w003:~/caravel_user_project_analog/verilog/dv/mprj_por$ make
/home/hayato/GCC/bin/riscv32-unknown-elf-gcc -I /home/hayato/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,- Bstatic,-T,/home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/sections. lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/home/hayato/GCC/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# Fix the base address of the flash
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/hayato/caravel_user_project_analog/pdk/sky130B \.
-I /verilog/rtl \.
-I /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/hayato/caravel_user_project_analog/caravel/verilog/ rtl˶ -I .
-I ... /I ... /... /... 
mprj_por_tb.v -o mprj_por.vvp
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: typ expression selected.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:343: error: missing module type: caravan_core
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:408: error: Unknown module type: copyright_block_a
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:409: error: Unknown module type: caravan_logo
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:410: error: Unknown module type: caravan_motto
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:411: error: Unknown module type: open_source
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:412: error: Unknown module type: user_id_textblock
Error 500 occurred during elaboration.
*** These modules were missing:
 caravan_core was referenced once.
 caravan_logo was referenced 1 time.
 caravan_motto was referenced 1 time.
 copyright_block_a was referenced 1 time.
 open_source has been referenced 1 times.
 user_id_textblock has been referenced 1 times.
***
make: *** [Makefile:51: mprj_por.vvp] error 244

【My Situation】 Run 「make」 in ~/caravel_user_project_analog/verilog/dv/mprj_por$. The following files are all located in /home/hayato/caravel_user_project_analog/caravel/verilog/rtl/. caravan_core.v caravan_core.v Copyright_block_a.v caravan_logo.v caravan_motto.v Open Source User_ID_textblock.v The following threads have been verified https://open-source-silicon.slack.com/archives/C02096M650E/p1676586848842409 I am running on a local install (Linux), not in a docker environment. I am using ubuntu 22.04 by wsl2. The PC is a corei7 with 16GB of RAM.

You would need to ask the openlane developers to be certain, but make sure that the "caravel" project has been pulled and exists in the

caravel/

path in the user project wrapper. If that's true, then the issue may be that the scripts have cloned the "lite" version of the caravel repository; I recall that there was an issue with using the "lite" version with the analog wrapper. But I'm not sure about that.

@hayato kimura In the log you posted, the

rtl

directory appears to have some strange characters

iverilog -DFUNCTIONAL -DSIM -I /home/hayato/caravel_user_project_analog/pdk/sky130B \.
-I /verilog/rtl \.
-I /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/hayato/caravel_user_project_analog/caravel/verilog/ rtl˶ -I .

before the

rtl

, there is a space and after the

rtl

, is the unicode 2 byte character U+02F6

˶

. Is this the Makefile you’re using? Have you changed the Makefile or directory names?

Thank you for your consideration. The caravel path is set as follows

export CARAVEL_ROOT=/home/hayato/caravel_user_project_analog/caravel

The paths are specified in the "caravel" folder that is created when Install Caravel is executed. caravel uses the normal version. I noticed a problem with the Lite version in the past, so I re-installed it. The

make

file was rewritten according to the following thread. Added

-I $(MCW_ROOT)/verilog/rtl" to line 52

. https://open-source-silicon.slack.com/archives/C02096M650E/p1676599146529199?thread_ts=1676586848.842409&cid=C02096M650E Just to be sure, I replaced it with a Makefile and ran it again, but it does not seem to be affected. The result of the "make" execution in that case is as follows.

hayato@md22w003:~/caravel_user_project_analog/verilog/dv/mprj_por$ make
/home/hayato/GCC/bin/riscv32-unknown-elf-gcc -I /home/hayato/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/home/hayato/GCC/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/hayato/caravel_user_project_analog/pdk/sky130B \
-I /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/hayato/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:343: error: Unknown module type: caravan_core
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:408: error: Unknown module type: copyright_block_a
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:409: error: Unknown module type: caravan_logo
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:410: error: Unknown module type: caravan_motto
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:411: error: Unknown module type: open_source
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:412: error: Unknown module type: user_id_textblock
500 error(s) during elaboration.
*** These modules were missing:
        caravan_core referenced 1 times.
        caravan_logo referenced 1 times.
        caravan_motto referenced 1 times.
        copyright_block_a referenced 1 times.
        open_source referenced 1 times.
        user_id_textblock referenced 1 times.
***
make: *** [Makefile:51: mprj_por.vvp] Error 244

@hayato kimura can you check that

caravan_core.v

is in

/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/

?

@Mitch Bailey I checked and

caravan_core.v

exists in

/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/

. Attached is a screenshot. There may be a problem with my environment, so I will now try to install WSL2 on another windows 11 PC to see if the same phenomenon can be reproduced.

@Marwan Abbas any thoughts?

Hi @hayato kimura, can you please try to add the missing modules to

mgmt_core_wrapper/verilog/includes/includes.rtl.caravel

and let me know if that works?

@Marwan Abbas The

mgmt_core_wrapper

was not found under the directory

caravel_user_project_analog

. Is this a problem? No hits on

find -iname "mgmt_core_wrapper"

.

Is

MCW_ROOT

set to anything?

@Mitch Bailey

MCW_ROOT

was not set. I am sorry, but I don't know how to set it up, could you please tell me which article I should refer to?

@hayato kimura Thanks for your patience. First let’s try adding these missing files

caravan_core.v
        caravan_logo.v
        caravan_motto.v
        copyright_block_a.v
        open_source.v
        user_id_textblock.v

to

$CARAVEL_ROOT/verilog/rtl/caravan_netlists.v

before

include caravan.v

. It that shows some progress, I’ll create a pull request. We may still need to do something with

MCW_ROOT

too. Do you have a

$CARAVEL_ROOT/mgmt_core_wrapper

directory?

@Mitch Bailey Thanks. As you advised, I rewrote the description of

caravan_netlists.v

and included 6 modules before

caravan.v

, which improved the situation. The following error then appeared, but was remedied by rewriting

caravan_core.v

and deleting the error line(184~223).

/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:84:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:184: error: 'gpio_in_core' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:85:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:185: error: 'gpio_mode0_core' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:86:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:186: error: 'gpio_mode1_core' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:87:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:187: error: 'gpio_outenb_core' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:88:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:188: error: 'gpio_inenb_core' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:89:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:191: error: 'mprj_io_inp_dis' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:110:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:192: error: 'mprj_io_oeb' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:109:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:193: error: 'mprj_io_ib_mode_sel' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:111:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:194: error: 'mprj_io_vtrip_sel' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:112:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:195: error: 'mprj_io_slow_sel' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:113:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:196: error: 'mprj_io_holdover' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:114:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:197: error: 'mprj_io_analog_en' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:115:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:198: error: 'mprj_io_analog_sel' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:116:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:199: error: 'mprj_io_analog_pol' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:117:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:200: error: 'mprj_io_dm' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:118:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:201: error: 'mprj_io_in' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:106:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:202: error: 'mprj_io_in_3v3' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:107:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:203: error: 'mprj_io_out' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:108:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:204: error: 'mprj_io_one' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:121:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:215: error: 'user_gpio_analog' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:125:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:216: error: 'user_gpio_noesd' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:126:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:219: error: 'user_clamp_high' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:128:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:220: error: 'user_clamp_low' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:129:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:223: error: 'user_analog' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:127:      : It was declared here as a net.

Then when I run make, the following error comes up next. I am trying to find a solution.

hayato@md22w003:~/caravel_user_project_analog/verilog/dv/mprj_por$ make
/home/hayato/GCC/bin/riscv32-unknown-elf-gcc -I /home/hayato/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/home/hayato/GCC/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/hayato/caravel_user_project_analog/pdk/sky130B \
-I /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/hayato/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: Choosing typ expression.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:291: warning: input port clock is coerced to inout.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/mgmt_core.v:8426: error: port ``vccd1'' is not a port of VexRiscv.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/mgmt_core.v:8426: error: port ``vssd1'' is not a port of VexRiscv.
../../../verilog/rtl/example_por.v:64: error: Net mid is not defined in this context.
../../../verilog/rtl/example_por.v:64: error: Output port expression must support continuous assignment.
../../../verilog/rtl/example_por.v:64:      : Port 1 (X) of sky130_fd_sc_hvl__schmittbuf_1 is connected to mid
../../../verilog/rtl/example_por.v:74: error: Unable to bind wire/reg/memory `mid' in `mprj_por_tb.uut.chip_core.mprj.mprj.por1'
../../../verilog/rtl/example_por.v:74: error: Failed to elaborate port expression.
../../../verilog/rtl/example_por.v:64: error: Net mid is not defined in this context.
../../../verilog/rtl/example_por.v:64: error: Output port expression must support continuous assignment.
../../../verilog/rtl/example_por.v:64:      : Port 1 (X) of sky130_fd_sc_hvl__schmittbuf_1 is connected to mid
../../../verilog/rtl/example_por.v:74: error: Unable to bind wire/reg/memory `mid' in `mprj_por_tb.uut.chip_core.mprj.mprj.por2'
../../../verilog/rtl/example_por.v:74: error: Failed to elaborate port expression.
10 error(s) during elaboration.
make: *** [Makefile:51: mprj_por.vvp] Error 10

@Marwan Abbas in

caravel_user_project_analog/verilog/dv/mprj_por

, does

make

work for you.

@Mitch Bailey I built a linux environment from scratch on another PC and tried. It seems like I have made some progress, but could you please confirm this? The path has already been set as follows. export GCC_PATH=/home/hayato/GCC/bin export GCC_PREFIX=riscv32-unknown-elf export PDK_ROOT=/home/hayato/pdk export PDK=sky130B export CARAVEL_ROOT=/home/hayato/caravel_user_project_analog/caravel export MCW_ROOT=/home/hayato/caravel_user_project_analog/mgmt_core_wrapper First, I just executed`hayato@md18w014:~/caravel_user_project_analog/verilog/dv/mprj_por$ make` , The following error was output.

/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_netlists.v:97: Include file mgmt_core_wrapper.v not found

So I did the following

hayato@md18w014:~/caravel_user_project_analog$ make install_mcw

I added

-I $(MCW_ROOT)/verilog/rtl

to line 52 of

/home/hayato/caravel_user_project_analog/verilog/dv/mprj_por/Makefile

and ran make again,　the following error was output.

/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:343: error: Unknown module type: caravan_core
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:408: error: Unknown module type: copyright_block_a
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:409: error: Unknown module type: caravan_logo
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:410: error: Unknown module type: caravan_motto
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:411: error: Unknown module type: open_source
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:412: error: Unknown module type: user_id_textblock

This is as I was told before, https://open-source-silicon.slack.com/archives/C01EX4ATEKF/p1689818275632859?thread_ts=1689605947.815399&cid=C01EX4ATEKF method solved the problem. When I run make again, I get the following error, unlike when I consulted before.

hayato@md18w014:~/caravel_user_project_analog/verilog/dv/mprj_por$ make
/home/hayato/GCC/bin/riscv32-unknown-elf-gcc -I /home/hayato/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/home/hayato/GCC/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/hayato/pdk/sky130B \
-I /home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl -I /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/hayato/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/hayato/pdk/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:220: error: 'user_clamp_low' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan_core.v:129:      : It was declared here as a net.
/home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core.v:four: error: 'mgmt_core' has already been declared in this scope.
/home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core.v:four:      : It was declared here as a module.
/home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core.v:8469: Module mgmt_core was already declared here: /home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core.v:4

make: *** [Makefile:51: mprj_por.vvp] Error 3
rm mprj_por.elf

I have tried everything, but I don't know how to deal with this, and I apologize for the trouble, but could you please check?

I’m not sure how much this version of caravan has been tested, so thanks for your reports. In line 129 of

caravel_core.v

, can you change

inout wire [2:0] user_clamp_low

to

inout [2:0] user_clamp_low

As for

mgmt_core

, can you show me a list of files that are being included? Maybe one of those has a

mgmt_core

definition too.

@Mitch Bailey Line 129 was corrected and the error was resolved. The following error was also resolved by reinstalling caravel_user_project_analog. (Sorry, not sure why.)

error: 'mgmt_core' has already been declared in this scope.

What about the following that have since come up?

/home/hayato/GCC/bin/riscv32-unknown-elf-gcc -I /home/hayato/caravel_user_project_analog/caravel -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,/home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/sections.lds,--strip-debug -ffreestanding -nostdlib -o mprj_por.elf /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel/start.s mprj_por.c
/home/hayato/GCC/bin/riscv32-unknown-elf-objcopy -O verilog mprj_por.elf mprj_por.hex
# to fix flash base address
sed -i 's/@10000000/@00000000/g' mprj_por.hex
iverilog -DFUNCTIONAL -DSIM -I /home/hayato/PDK/sky130B \
-I /home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl -I /home/hayato/caravel_user_project_analog/caravel/verilog/dv/caravel -I /home/hayato/caravel_user_project_analog/caravel/verilog/rtl \
-I ../    -I ../../../verilog/rtl \
mprj_por_tb.v -o mprj_por.vvp
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11378: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11379: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11380: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11381: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/hayato/PDK/sky130B/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v:11382: warning: choosing typ expression.
/home/hayato/caravel_user_project_analog/caravel/verilog/rtl/caravan.v:291: warning: input port clock is coerced to inout.
/home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core.v:8426: error: port ``vccd1'' is not a port of VexRiscv.
/home/hayato/caravel_user_project_analog/mgmt_core_wrapper/verilog/rtl/mgmt_core.v:8426: error: port ``vssd1'' is not a port of VexRiscv.
2 error(s) during elaboration.
make: *** [Makefile:51: mprj_por.vvp] Error 2
rm mprj_por.elf

The simplest temporary solution is probably changing the following at line 8426 of

mgmt_core_wrapper/verilog/rtl/mgmt_core.v

VexRiscv VexRiscv(
`ifdef USE_POWER_PINS
    .vccd1(VPWR),
    .vssd1(VGND),
`endif
        .clk(sys_clk),

to

VexRiscv VexRiscv(
        .clk(sys_clk),

I don’t know why it’s running the simulation with

USE_POWER_PINS

or why the definition of

VexRiscv

does not have the

USE_POWER_PINS

directive, but maybe the above change will work.

@hayato kimura are you including

VexRiscv_MinDebugCache.v

? Can you please show me your includes file after your modifications?

@Mitch Bailey As attached, the problem has been resolved. I believe it is working fine. Thank you very much. @Marwan Abbas Is the includes file correct

mgmt_core.v

? Attached.

@hayato kimura If you could please create an issue and state the fixes you did, in order to fix it. Thank you for your patience.

@Marwan Abbas Yes, I understand. Sorry for the rudimentary question, where and how should I create an "issue"?

If you go here https://github.com/efabless/caravel_user_project_analog/issues/new, you can add a title and description of the issue, and how you fixed it. Then click on

Submit new issue

.

Sorry for the delay, we are planning to create an issue, so please wait a bit.