Hello Everyone, I am running my Verilog code using...
# openroad
d
Hello Everyone, I am running my Verilog code using openroad flow for RTL2GDS. I got this error(attached image) in floorplan stage. I did not get what needs to be done to debug the strap width issue with metal 4? Any suggestions??
m
Maybe use a fixed die area in the
config.json
file? Example
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"DIE_AREA"                 : "0 0 900 600",
d
@Mitch Bailey, it have added this in my config... same issue still persists
v
@Deepak Are you using latest ORFS?
d
I have installed it two months back
v
Update once try again. Same problem mean share a test case by running
make pdn_issue
d
ok will update you after updating ORFS
pdn_ripple_sky130hd_base_2023-07-13_18-46.zip
m
Its a very small design. 'export CORE_UTILIZATION = 1' solves your problem (instead of your 'export CORE_UTILIZATION = 60'). Alternatively, you can leave CORE_ULITIZATION undefined.
v
@Deepak Can you share your
<http://config.mk|config.mk>
it is tiny design. It has only 2 std cells. If you go with CORE_UTILIZATION it size only 8x8um. It is not valid to place power grid with default flow. So comment that variable and use
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export DIE_AREA   = 0 0 100 100
export CORE_AREA  = 10 10 90 90
in
<http://config.mk|config.mk>
and run the flow again
seems you define
export CORE_AREA='100 100 900 900'
, but automated flow give priority to
CORE_UTILIZATION
variable. So remove this from
<http://config.mk|config.mk>
and try again with only
DIE_AREA
and
CORE_AREA
variables
d
okay, Now i have put these in config file and commented DIE AREA and CORE AREA ,it is running the flow till end
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export CORE_UTILIZATION  = 30
export CORE_ASPECT_RATIO = 1
export CORE_MARGIN       = 2
export PLACE_DENSITY     = 0.70
Thanks @ @Vijayan Krishnan, @Michael Strothjohann