Hi, I'm wondering whether the AI-generated code should be Verilog. Are other languages like Chisel acceptable?

not sure what is this in reference to. Skywater130 does not have such restrictions and OpenLane will eat any verilog Yosys would eat, does not matter if chisel generated or not.

Specifically, I assume it is in reference to the announced second generative AI silicon challenge. And no, it does not have to be verilog. It just needs to be generated by an AI and be synthesizable to an ASIC target. Given that the LLMs are very context-limited, generating large and complex systems probably requires moving to as high-level a description level as you can, so Chisel is probably a good choice.

@Tim Edwards Thanks for your reply! I'm moving from Verilog to Chisel/Firrtl, and things seem to be easier than before.

Also, the more different approaches people take, the more ground we cover for understanding how the LLMs work best for generating hardware.