@Tim Edwards Hello Tim, thanks for helping Ellen with the work. I have a question also about the skywater spice models. I noticed they dont allow width less than 0.42u which is strange, and Im porting some TMSC 0.18u where 0.24u width is allowed. Some transistors just need the weakest pullup but want to be fast, so I didnt want to make a longer channel. On the other extreme, I am not totally confident about the results I get with large mos capacitors e.g. L>4u and W>4u to save area. I find the spice results are showing lower capacitance than the TSMC 0.18u by about 2:1. Did skywater ever take up your offer to to model binning? Does anyone have experience of measured results vs. spice for these kind of devices with W and L on the limits of the models? Thank you, John

Yes, well, TSMC has particularly good processes. And as you know, some foundries fudge their feature size numbers; there are no gate lengths in sky130 less than 0.15um, and there is no mask shrinking involved, so it's not really a 130nm process. Of the SRAM devices, though, there are ones with width 0.21um and others with width 0.14um, but they did not allow those rules for design outside the SRAM cores.

Thanks Tim. sorry, im not used to slack which sends as soon as you do <CR> so my message was broken up a few times. What range of width and lengths do you think the Skywater models could be trusted with? I could always break the mos caps up into smaller pieces.

There are models that are characterized at specific widths and lengths, which can be determined by the narrow range of

wmin

,

wmax

,

lmin

, and

lmax

parameters in the model. If you stick with those widths and lengths, the characterization should be good. Between those devices, there is a lot of debate about whether the interpolated characterization can be trusted.