I am getting a magic DRC violation(for only 1 transistor) showing "all nwells must contain metal connected N+ taps" while running openlane flow for user_project_wrapper in integrating my design with caravel. How to resolve the above issue?

psubstrate/nwells must be connected via tap to metal. Can you share your layout?

layout_caravel.png,config_final.json

Looks like you may have tried to tie some of the inputs either high or low at the

user_project_wrapper

level. This causes openlane to place a

conb

cell but since

"SYNTH_ELABORATE_ONLY": 1,

, it doesn’t get placed in a powered standard cell row. I think what you want to do is tie all your inputs at the

user_proj_example

level and use the default

verilog/rtl/user_project_wrapper.v

. Anyone have any other ideas?

I have done the same. I didn't modify user_projrct_wrapper . Could you please tell me how to tie all the inputs ate the user_pro_example level?

@Manikanta Neralla Sorry for the irrelevant advice. Comparing your config to other taped out designs, I notice that you have

"CLOCK_TREE_SYNTH": 1,

where it’s normally

0

. Does that make a difference?

Ok sir. I will keep it 0 and try it.

Can you share your

verilog/gl/user*.v

files?

user_proj_example.nl.v,user_proj_example.v,user_project_wrapper.nl.v,user_project_wrapper.v

Looking at the gate level verilog, it looks like yosys is adding low connections to undefined inputs. See

io_in

below. You could t

sky130_fd_sc_hd__conb_1 TIE_ZERO_zero_ (.VGND(vssd1),
    .VNB(vssd1),
    .VPB(vccd1),
    .VPWR(vccd1),
    .LO(zero_));
 user_proj_example mprj (.vccd1(vccd1),
    .vssd1(vssd1),
    .wb_clk_i(wb_clk_i),
    .wb_rst_i(wb_rst_i),
    .wbs_ack_o(wbs_ack_o),
    .wbs_cyc_i(wbs_cyc_i),
    .wbs_stb_i(wbs_stb_i),
    .wbs_we_i(wbs_we_i),
    .io_in({zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    zero_,
    io_in[37],
    io_in[36],
    io_in[35],
    io_in[34],
    io_in[33],
    io_in[32],
    io_in[31],
    io_in[30],
    io_in[7],
    io_in[6],
    io_in[5],
    io_in[4],
    io_in[3],
    io_in[2],
    io_in[1],
    io_in[0]}),

The rtl only has the lower 16 bits assigned.

.io_in ({io_in[37:30],io_in[7:0]}),
    .io_out({io_out[37:30],io_out[7:0]}),
    .io_oeb({io_oeb[37:30],io_oeb[7:0]}),

You could try assigning the upper 22 bits to

io_in[29:8]

. Right now, the

user_proj_example.v

rtl has

wire [0:15] inp,outp;

and

assign inp=io_in[`MPRJ_IO_PADS-1:`MPRJ_IO_PADS-16];
 assign io_out[`MPRJ_IO_PADS-1:22]=outp;

which is

inp [0:15] = io_in[37:22]

This looks like it reversing the bit order (may not be a problem) and using the unassigned (zero) values from the high bits of

io_in.

which 22 bits I need to assign to io_in[29:8]? could you please elaborate?

I’m not really familiar with verilog, but what about using the default

verilog/rtl/user_project_wrapper.v

and then using these assignment statements in

verilog/rtl/user_proj_example.v

.

assign inp={io_in[37:30],io_in[7:0]};
 assign {io_out[37:30],io_out[7:0]}=outp;

Are using the same gpio for input and output? If you are, you need to set

io_oeb

low for the bits you what to output.

yes sir, I am using the default user_project_wrapper. I have done assignment as above in user_proj_example.

Ok. Sorry, my mistake. You are using the default

user_project_wrapper.v

. Your

user_proj_example

bus widths are too long. Default

user_proj_example

input  [15:0] io_in,
    output [15:0] io_out,
    output [15:0] io_oeb,

Your

user_proj_example

input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,

The extra bits are being set to zero which causes the conb cell to be added and creates the drc error. The io_oeb signals are set like this in the the default

user_proj_example

assign io_oeb = {(14){rst}};

Ok sir. I will try the above and let you know the status.

Sorry, I don’t know. Anyone know how to get rid of slew and max capacitance warnings? I image it has to do with these settings in

user_proj_example/config.json

.

"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
    "PL_RESIZER_MAX_SLEW_MARGIN": 50,
    "GLB_RESIZER_MAX_SLEW_MARGIN": 50,
    "GLB_RESIZER_SETUP_SLACK_MARGIN": 0.2,

Ok sir

Can you post your

verilog/dv/DMT_testbench/Makefile

? Looks like it can’t figure out how to make

DMT_testbench.vcd

. Is that something you need to provide?

Makefile

What’s

MCW_ROOT

set to? Is there anything in the directory? Did you run

make install_mcw

?

no sir. MCW_ROOT set to mgmt_core_wrapper directory sir.

install_mcw

should have been done as part of

make setup

. If there is nothing in the

MCW_ROOT

directory, you should be able to run

make install_mcw

. Just be sure that

MCW_ROOT

is an absolute directory.

Sir, I am unable to run full chip simulation by following the procedure mentioned in the caravel documentation. Is there any other resource from where I can learn how to run full chip simulation?

There may have been some changes. Make sure you’re using the most recent versions of the test benches. Also ask here #caravel.