Hi, could you help me with this issue, I tried before change the names of power pins from VPWR and VGND to vccd1 and vssd1, also i check fail log of step five but doesnt save a register on wich fail.

[STEP 5]
[INFO]: Running Tap/Decap Insertion (log: designs/full_adder/runs/RUN_2023.06.21_19.09.09/logs/floorplan/5-tap.log)...
[ERROR]: VDD_NETS and GND_NETS must *both* either be defined or undefined
[ERROR]: Step 5 (floorplan) failed with error:
-code 1 -level 0 -errorcode NONE -errorinfo {
    while executing
"throw_error"
    (procedure "run_power_grid_generation" line 7)
    invoked from within
"run_power_grid_generation"
    (procedure "run_floorplan" line 56)
    invoked from within
"run_floorplan"} -errorline 1

this are my config file

{
  "DESIGN_NAME": "full_adder",
  "VERILOG_FILES": "dir::src/full_adder.v",
  "CLOCK_PORT": null,
  "DESIGN_IS_CORE": false,
  "FP_SIZING": "absolute",
  "DIE_AREA": "0 0 100 100",
  "CORE_AREA": "3 3 97 97",
  "FP_CORE_UTIL": 90,
  "PL_BASIC_PLACEMENT": 1,
  "FP_PDN_HPITCH": 10,
  "FP_PDN_VPITCH": 15,
  "FP_PDN_HOFFSET": 2,
  "FP_PDN_VOFFSET": 2,
  "FP_IO_HLENGTH": 2,
  "FP_IO_VLENGTH": 2,
  "RT_MAX_LAYER": "met4",
  "FP_PDN_CORE_RING": false,
  "SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
  "VDD_NETS": "VPWR",
  "GNN_NETS": "VGND"
}

and this are my module description

/// sta-blackbox

`define USE_POWER_PINS 

module full_adder(
    `ifdef USE_POWER_PINS
    inout VPWR,
    inout VGND,
    `endif
    input A,
    input B,
    input C_IN,
    output SUM,
    output C_OUT

);

"GNN_NETS" : "VGND"

should be GND_NETS - just a simple typo

Thanks a lot Jecel Assumpção Jr the problem has been solved with that