https://open-source-silicon.dev logo
Join Slack
Powered by
<@U016EM8L91B> can I get a quick sanity check on t...
# mpw-3-silicon
m
@Tim Edwards can I get a quick sanity check on the DLL
I'm trying to get 31.66 M
from a 10M clock
which I think is possible by setting
image.png
this is currently making no difference to the clock, so wondering if I've got something wrong
image.png
t
What's your exfernal clock rate?
m
10M
t
The feedback divider is too high for that external clock. The feedback divider value times the external clock = the DCO frequency. The range of the DCO is about 50 to 100 MHz.
Actually more like 80 MHz to 150 MHz---Depends on the voltage.
m
ok, so need to supply an external clock if I want < 50M.
would be cool if you could take a look at this sometime: https://github.com/kbeckmann/caravel-pll-calculator
t
How exact do you need the frequency to be? 30 or 40 MHz is easy to hit (90 / 3 and 80 / 2, respectively).
31.66 is easy to hit if you have a 5 MHz external clock; you can then run the DCO at 95 MHz and divide by 3 for the output.
I really should have implemented a fractional divider. . .
m
yeah I can make a 5M external clock
I can even tune it to get exactly 31.5
which I need for the vga clock
t
It occurs to me that I was never able to get the DLL to run on the MPW-2 silicon. A hold violation in the housekeeping prevented the "DLL enable" and "DCO enable" bits from being different---they could either be both zero or both one, preventing the DLL from operating as anything but a DCO. Operation as a DCO might work well enough for your needs, though. The frequency is not particularly stable, but the drift should be pretty slow, meaning that you can manually set the DCO trim and the output divider to get reasonably close to your target 31.5 MHz.
There is always some possibility that the DLL works on MPW-3, but given that we didn't resynthesize the SoC between MPW-2 and MPW-3, I think that's a pretty low probability.
m
Thanks for the heads up
Open in Slack
PreviousNext
Powered by