There are a few big barriers, we'd need a much better understanding of the proposed architecture and who is paying for what. My largest concern is data rates available on the SKY130 process. I do not think anybody has implemented the full USB-C 3.1 5GB/S or 3.2 10GB/S phy on SKY130. Also building a multi chip module architecture costs a lot in power and latency and clock domain crosssing complexity and it might not achieve what you want. The idea of a MCM with Caravels or a similar but higher IO device is interesting for sure.