Hi, I was ploting the noise density for nmos and pmos devices (to determine the corner frequency), the nmos looked ok but the pmos has a rise at the end of the frequency spectrum, if someone had any ideas of what can be happening i would appreciate it. (image of the pmos plot)

Show us your testbench and your spice netlist, so we can help.

** sch_path: /foss/designs/IPD413_2023_HW2_git-main/mos-noise-corners_jm.sch **.subckt mos-noise-corners_jm g1 d1 *.ipin g1 *.iopin d1 XM1 GND g1 d1 d1 sky130_fd_pr__pfet_01v8_lvt L=0.35 W=1 nf=1 ad='int((nf+1)/2) * W/nf * 0.29' as='int((nf+2)/2) * W/nf * 0.29' + pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)' nrd='0.29 / W' nrs='0.29 / W' + sa=0 sb=0 sd=0 mult=1 m=1 ** begin user architecture code .lib /foss/pdks/sky130A/libs.tech/ngspice/sky130.lib.spice tt .option wnflag = 1 scale=1e-6 vgs g1 0 dc=0.9 ac=1 vds d1 0 dc=0.9 hout io 0 vds 1 .control save all set sqrnoise noise v(io) vgs dec 100 1 100G setplot noise1 plot 10*log10(onoise_spectrum) setplot noise2 print onoise_total .endc ** end user architecture code **.ends .GLOBAL GND .end

It is exactly that. I think the input referred noise must be different. I see that you use a voltage source at the output and a current controlled voltage source to output it. Maybe you could select vds as the output voltage source and the simulation will output the current noise. Normally, the transistor output will be connected to a capacitor, and it attenuates the high frequency noise. I really don't know what is happening there. I'll try your circuit here.

I may be mistaken but it looks like your device is OFF. Just to be clear, it’s a PFET device Vgs = 0V (Vg = 0.9V, Vs = 0.9V, Vb = 0.9V)