Can we perform pnr in between SRAM macros? Like in modern designs using openlane?

It is possible to manually or automatically place hard macros and route using openlane. You need to specify the power connections with

FP_PDN_MACRO_HOOKS

. Your results may not be as good as commercial tools.

i know about that, what I meant was that is itpossible to perform placement as well as routing when connecting multiple macros, for example infering standard cells in the top verilog file whwn we are connecting SRAM macros

Yes we can do that.

How is it done? Because I couldn't get to work, it fails at the first STA pass

How does it fail? (More info is needed...) Sounds like a constraint or clock definition problem