@Tim Edwards Is there a possibility in magic to mark a metal capacitor structure, so that when extracting a netlist for LVS, that this cap is written into the netlist? Something like a marker layer for metal caps.

@Harald Pretl I believe the vertical mim_capacitors are already extracted. Are you referring to a lateral metal capacitor like this? I had a modified tech file that would extract these as capacitors with an L/W corresponding to the size of the space between metal2.

Yes, exactly. This type of caps are very common in analog design, and I think about how to cleanly make them work. Either, remove them from the SCH netlist, or put them into the LAY netlist. Both works, and we need a mechanism for that.

I added a new type to the schematic and a

CAPID

layer over the entire layout metal area. The mom capacitors were extracted as

CAPID NOT metal2

. It’s not that big of a change, but we probably need a different

CAPID

layer for each metal layer. Probably should come up with some sane DRC rules too.

@Harald Pretl: Put the device in a subcircuit and give it a property called "device" with a value string equal to what the output line in the .ext file should look like. Make sure you have pins on the terminals.

@Tim Edwards I think that might be a bit difficult in this situation. In the above example each “device subcircuit” would consist of only 2 metal wires which would be the device pins. There are 36 devices above, so 34 of the terminals would overlap. Since there are only 2 shapes in the sub cell, these cells would most likely be flattened when read in from GDS, thus causing the final LVS to fail.

@Mitch Bailey: It could be a single device with 19 terminals, although I've never tried using "device subcircuit" with so many terminals, so it might break some array limit somewhere. It could also be done by black-boxing the subcell and providing the subcircuit netlist from a manually generated file when running simulation or LVS.

@Tim Edwards thanks for the hint, will try that.