hello everyone, i m working on Phase frequency detector for PLL, but i dont know how i ca evalute it or calculate the power cumsumption and the phase noise, i need help please

Do you have a working circuit already? Power consumption is straightforward. Phase noise is difficult, because, as far as I know, there is no transient noise simulations for the current open source flow.

@Luis Henrique Rodovalho ngspice has transient noise simulation but it's not like SST simulation in the commercial tools. Also, I don't believe it's fully qualified. @Rafik Bouch Please check our attempt to design a full PLL using Open Source tools here: https://github.com/mabrains/PLL_design Check this: https://github.com/mabrains/PLL_design/blob/a6a3f784f15fda675b60afa626cd00bf4ddda9[…]d_Elshahat/phase_nosie_analysis/CMOS_VCO_PN2/phaseNoise_calc.py And This: https://github.com/mabrains/PLL_design/blob/a6a3f784f15fda675b60afa626cd00bf4ddda9[…]at/phase_nosie_analysis/CMOS_VCO_PN2/VCO_Full_Phase_Noise.spice

@Amro Tork Impressive work! A true mixed signal project! The only thing that I missed there were individual power domains for each block. There is already a bandgap reference. LDOs wouldn't be hard to implement from there.

@Luis Henrique Rodovalho Thanks for the feedback. I was hoping to get this project to completion and have a full Bluetooth and Wifi PLL IP available open source and the team of students would write a paper on it. Hopefully someone would work with us on this.

Hey, I've just realized it is just the phase detector, not the entire PLL! Well, you should measure the rise and fall times of your signal and also the width of your reset pulse. The phase detector power consumption is a blip in the total PLL power consumption, as it work at the slower frequency of the reference clock. Phase noise is tricky... what you have to do is to calculate the noise of the charge pump when both up and down signals are on. When the PLL is locked, up and down signals are very short, and the charge pump with contribute to the system noise only during the reset pulse. So, you run the AC noise for this condition, integrate it in the right frequency range, and divide it for the duration of the reset pulse over the reference clock period.

@Luis Henrique Rodovalho It’s the entire PLL. But I shared on example, you could check the rest of the repo.

@Amro Tork Amazing! Really good design! And everything is there for us to learn about! I really didn't know that ngspice behaviorial models could be so easy, after working with Verilog-A.

@Luis Henrique Rodovalho Anytime

Ok, I actually work designing PLL parts at my job, but I know very little beyond basics at system level. I have a few suggestions that may be useful: 1. The bandgap current reference seems off... as it stops working at some corners. I hope it is only convergence problems, but, if it is not, it means your circuit can stop working because the charge pump won't deliver its current. I would put an option for an external current, and, if possible, an additional mirror to probe it's output outside. 2. The charge pump sense amplifier seems to have full input range. Does it need to be? 3. The charge pump behavioral model is made with resistors. Not cool to use it before a passive loop filter. 4. The PFD behavioral model uses pico-seconds fall and rise times. Dos the real circuit behave this way? 5. Is there a buffer between the PHD and the CP? How does you make the up/dn and its inverted signals? 6. Is the buffer after the VCO just an inverter gate? No decoupling caps? 7. Maybe you should use coarse caps in the VCO for calibration. And you should have an option to measure it in a open loop configuration.

1. We believe that’s a models issue. BTW, I don’t believe the models are working correctly for Sky130nm. 2. Need to look into this. 3. We used and ideal resistor with equation to make sure the current matches the CP driving capabilities. But we could entertain other options like voltage controlled current sources. Actually we have tested this but didn’t lead us to working model. And due to time crunch and NGSpice weird behavior we ended up using resistor model. 4. No those values are just placeholders and we kind of change them in the run script here: https://github.com/mabrains/PLL_design/blob/main/pll_int/PFD/testbench/scripts/analysis/run_pfd_behav.py 5. Are you asking about the actual circuit or behavioral model? 6. We added 2 inverters to make sure that the output is rail to rail for the fractional divider to work. No we didn’t add decoupling caps. 7. We tried to use caps from PDK. We faced multiple issues. I think they are related to the models of MIM caps. Few final notes, this effort was funded by Mabrains and it was done by a group of 7 brilliant grads and supervised by one of Prof. Razavi’s students. Unfortunately, I had to stop the project before finalizing it, due to budget cuts. There were many steps that I thought were needed to complete the design. But I think over all the team was going into the right directions even though the hurdles we faced while using NGSPICE. I’m hoping that someone might be able to contribute to that work to get it ready. My advise is to use GF180MCU models as we have spent more time qualifying that one I believe.

I would love to contribute to the project if someone continue from where it stopped. This project documentation is great, and I've never seen a mixed-signal system as complex as that with the open source. The charge pump behavioral is quite simple. Here is an example

@Luis Henrique Rodovalho I’m happy to hear that. Doing a PR on the repo would be great. Also, we could start finding people whom may be interested in joining that effort.