We just found one interesting issue: The AI's have generated code where several different parts are driving the same single-port SRAM block. The problems we faced is that IVerilog does not warn you and seems to find a way to simulate that anyway and the simulation results seem as if everything is ok. And then Yosys also does not warn of that issue and simply optimizes all that stuff away. So we either want to add warnings for such issues to both Iverilog and Yosys, or we want to develop a Verilog linting tool that detects such AI mishaps. Posted in #generative-ai-silicon-challenge