Hi @Tim Edwards @Mitch Bailey Can you please guide to check the source of mismatch her? I used the following commands to generate the spice file from the layout

select top cell

flatten -doinplace dac_3v_8bit_0

flatten -doinplace sbamuxm4_0

extract do local

extract all

ext2spice lvs

ext2spice

Thanks in advance

@Ahmed Reda Your netlist

sbamuxm4

vss

is connected to the top

vss

in the schematic, but connected to

dvss

in the layout.

** sch_path: /home/ahmedreda/Project/AR_SAR_ADC/ADC/xschem/adc_8ch_v1/adc_8ch_v4.sch
.subckt adc_8ch_v4 dvdd hold vdd vss dvss ena cmp vhigh vlow dac_out b0 b1 b2 b3 b4 b5 b6 b7 vdd1p8
+ inp[7] inp[6] inp[5] inp[4] inp[3] inp[2] inp[1] inp[0] in[2] in[1] in[0]
*.PININFO dvdd:B hold:I vdd:B vss:B dvss:B ena:I cmp:O vhigh:I vlow:I dac_out:O b0:I b1:I b2:I b3:I
*+ b4:I b5:I b6:I b7:I vdd1p8:B inp[7:0]:B in[2:0]:B
x1 dvdd dvss hold vdd net1 net2 ena vss sample_and_hold
x2 cmp dvdd dvss vdd vss net1 dac_out comparator_top
x3 dvdd vss dvss vdd b0 vhigh b1 b2 b3 dac_out b4 b5 ena b6 b7 vlow dac_3v_8bit
x4 vdd1p8 vss net2 inp[7] inp[6] inp[5] inp[4] inp[3] inp[2] inp[1] inp[0] in[2] in[1] in[0] sbamux4
.ends

@Mitch Bailey I got it. Thanks