Hello everyone, I wanted to ask about the 130 hs cells. There appear to be syntax errors in some of the Verilog models. For example sky130_fd_sc_hs__a22o.behavioral.v line 58 has "wire B2 and0_out;" The port names somehow sneaked into internal wires declarations. This happens in multiple places across the set. Also it seems that the repo for hs cells is already archived. Does that mean no more updates?

@Tomasz Chadzynski Even though the skywater repo has been archived, @Tim Edwards’ open_pdks does post processing to patch the known problems when creating the actual pdks used in openlane.

@Mitch Bailey Thank you, that is a very good point. I am trying to reach the maintainer of the original repo to see if it is possible to reopen it. It seems more straightforward this way. No need to maintain separate copies of the verilog models in open_pdks. If that can't happen then patching in open_pdks would be the next best choice. I am fairly new the this PDK was hs set not used for any reason? Verilator lint over the combined set from open_pdks reports 81 of this type of errors. More importantly, how were these models generated in the first place, was it by hand or from some tool? My point here is, is the problem just in the Verilog models or could it be a part of a bigger issue.

@Tomasz Chadzynski Thanks again for reporting the problem. So far, the skywater open-mpw designs have used (almost) exclusively

sky130_fd_sc_hd

. Unfortunately, I don’t know much more that that.