I'm sort of confused what's going on with the SPICE decks for the sky130 standard cells, some of the FETs seem to have drain and source swapped relative to what I'd expect. Take a look at the definition of the 2-input NAND gate (from

libraries/sky130_fd_sc_hd/latest/cells/nand2/sky130_fd_sc_hd__nand2_1.spice

):

.subckt sky130_fd_sc_hd__nand2_1 A B VGND VNB VPB VPWR Y
X0 Y A VPWR VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X1 VPWR B Y VPB sky130_fd_pr__pfet_01v8_hvt w=1e+06u l=150000u
X2 VGND B a_113_47# VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
X3 a_113_47# A Y VNB sky130_fd_pr__nfet_01v8 w=650000u l=150000u
.ends

Note that

sky130_fd_pr__pfet_01v8_hvt

defines its args in the order: drain, gate, source, body. So, FET X0 makes sense as a pull-up for A=0, because its drain is the output. But FET X1 seems backwards, why is VPWR the drain, and Y the source, not the other way around? I have the same confusion with the pull-down stack of X2 and X3, although at least there symmetry is broken between the two FETs. But in the pull-up case I can't see what breaks symmetry between the A and B inputs, and why one FET would be backwards relative to the other.

Drain and source of FETs are interchangeable. If there is no special doping on drain or source, then the extraction engine can't tell which is which without information that is not available in the layout (namely, direction of current flow). This should make no difference for simulation, and the LVS setup can specify that source and drain are permutable.