GitHub
05/20/2023, 4:21 PM1.5.253
Here's the schematic
ps-resistor▾
sky130_fd_pr__res_xhigh_po:4 vs. bgr_sym:1/sky130_fd_pr__res_xhigh_po:R5:
w circuit1: 36.57 circuit2: 37.26 (delta=1.87%, cutoff=1%)
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance sky130_fd_pr__res_xhigh_po:4 network:
l = 27
w = 36.57
M = 1
+
l = 27
w = 0.69
Circuit 2 instance bgr_sym:1/sky130_fd_pr__res_xhigh_po:R5 network:
m = 1
mult = 1
L = 27
W = 37.26
sky130_fd_pr__res_xhigh_po:5 vs. sky130_fd_pr__res_xhigh_po:R2:
w circuit1: 6.9 circuit2: 7.59 (delta=9.52%, cutoff=1%)
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance sky130_fd_pr__res_xhigh_po:5 network:
l = 24
w = 6.9
M = 1
+
l = 24
w = 0.69
Circuit 2 instance sky130_fd_pr__res_xhigh_po:R2 network:
m = 1
mult = 3
L = 24
W = 7.59
sky130_fd_pr__res_xhigh_po:12 vs. sky130_fd_pr__res_xhigh_po:R1:
w circuit1: 3.45 circuit2: 4.14 (delta=18.2%, cutoff=1%)
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance sky130_fd_pr__res_xhigh_po:12 network:
l = 24
w = 3.45
M = 1
+
l = 24
w = 0.69
Circuit 2 instance sky130_fd_pr__res_xhigh_po:R1 network:
m = 1
mult = 2
L = 24
W = 4.14
sky130_fd_pr__res_xhigh_po:7 vs. bgr_sym:1/sky130_fd_pr__res_xhigh_po:R6:
w circuit1: 10.35 circuit2: 11.04 (delta=6.45%, cutoff=1%)
Circuit 2 parallel/series network does not match Circuit 1
Circuit 1 instance sky130_fd_pr__res_xhigh_po:7 network:
l = 27
w = 10.35
M = 1
+
l = 27
w = 0.69
Circuit 2 instance bgr_sym:1/sky130_fd_pr__res_xhigh_po:R6 network:
m = 1
mult = 1
L = 27
W = 11.04
Looks like the source side might be merging series resistors with w
values that don't match.
Parallel resistors merge if l
is equal by adding w
and series resistors merge if w
is equal by adding l
, correct?
Test data is in test_lpo1
here.
RTimothyEdwards/netgen