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p

Pritesh Ps

05/19/2023, 8:29 PM
Hi, I'm trying to design step up switch capacitor converter. Which takes 1.5V as input and gives 4.5V as output. Operating frequency is 1kHz with 50% duty cycle. I have attached pics for the design. the input frequency is fed to the non-overlapping clock generator and then used to switch mosfets. can someone help me with my master's project, please. I have tried to change capacitor values, adding some load but didn't got as expected.
m

Mitch Bailey

05/19/2023, 9:46 PM
@Pritesh Ps If you’re using devices that will see voltage differences greater that 1.8v, you should use the 5V version of the logic from the
hvl
library.
p

Pritesh Ps

05/19/2023, 10:15 PM
I'm using 20v pmos from 'fd_sc_hd' library which comes with xschem + ngspice+ sky130. I'm not aware of hvl library and also how to include it for simulation.
m

Mitch Bailey

05/19/2023, 10:42 PM
Great! The discrete mosfets look ok. How about the standard logic cells. There’s a property on the logic symbols indicating the library. You can change that from
hd
to
hvl
. The
hvl
library is included in the standard
volare
pdks. I imagine you can just add another include line, replacing the 2
fd_sc_hd
with
fd_sc_hvl
.
l

Luis Henrique Rodovalho

05/19/2023, 10:58 PM
Use 5V devices. They are enough and more versatile. You will need buffers for your non-overlap clocks. If you want a 4.5 V output, you may need more rectifier steps.
Try to use ideal non-overlap clocks first. Sometimes, the gap between the non overlap clocks isn't enough for the simulation.
I recommend you trying a simple dickson charge pump first. I'm not sure your PMOS devices have properly biased substrates. It can adversely affect your cirucit.
👍 2
p

Pritesh Ps

05/20/2023, 3:10 PM
@Mitch Bailey Thank for the library suggestion. however After changing it, it doesn't getting recognized in simulation. Am I doing anything wrong?
m

Mitch Bailey

05/20/2023, 4:24 PM
I think you need to change the prefix in the xschem property window from
sky130_fs_sc_hd__
to
sky130_fd_sc_hvl__
.
p

Pritesh Ps

05/20/2023, 5:31 PM
@Mitch Bailey yes it worked. thanks again.
👍 1
@Luis Henrique Rodovalho thanks for the suggestions. I have tried to use nfet_05v0_nvt but it shows error during simulation as, model issue.
I also tried to remove VSS voltage supply node and put GND for VGND & VNB in digital cells. Also tried to change nmos L to 0.5 thinking sometimes it throughs error for 'could not find a valid model name', but still it is same.
ok. I will start with dicksons multiplier, along side with this.
l

Luis Henrique Rodovalho

05/20/2023, 10:10 PM
You're using nvt transistors. Maybe it is the problem. I'm not sure also if native NMOS transistors have isolated substrates in this technology. Additionally, 5V transistors can't have lengths below 0.5 um. Is there a symbol with the bulk terminal available? you should use them.