hello all, so i made this layout of the pmos lvt d...
# analog-design
m
hello all, so i made this layout of the pmos lvt device with W=1um L=0.35um NF=16 M=6 , and i'm trying to do LVS but i get this result when i try to run it, can anyone help me? Note: for the layout of the PMOS, i pulled the device from the devices1 menu and just connected all the drains with all the gates making it diode connected through metal1 and all the sources together through metal2.
t
What do the netlists look like? And how did you invoke netgen on the command line?
m
message has been deleted
PMOS2.spice is the spice generated from Magic and PMOS_tb.spice is the spice generated from xschem.
m
Try
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netgen -batch lvs "PMOS2.spice PMOS2" "pmos_tb.spice pmos_tb" /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
The second parameter in the netlist specification is the cell name to compare. Your extracted netlist has capacitors which probably aren’t needed for LVS. What commands did you use to extract the layout?
m
I did extract all then ext2spice lvs then ext2spice
m
Before
extract all
, can you do
Copy code
extract no all
extract do local
extract no all
turns off all the extraction options.
m
will try now.
So I don’t do extract all or i do it after extract do local?
I tried both and same problem.
here's the spice file now
m
Great! No more capacitances in the extracted layout. Do you get the same LVS results with the command I suggested?
m
yes, here's what i get when i type the Netgen command: netgen -batch lvs "PMOS2.spice" "pmos_tb.spice" /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl Netgen 1.5.242 compiled on Sun Dec 11 233933 EET 2022 Warning: netgen command 'format' use fully-qualified name ':netgen:format' Warning: netgen command 'global' use fully-qualified name ':netgen:global' Reading netlist file PMOS2.spice Call to undefined subcircuit sky130_fd_pr__pfet_01v8_lvt Creating placeholder cell definition. Reading netlist file pmos_tb.spice Reading setup file /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl No property as found for device sky130_fd_pr__pfet_01v8_lvt No property ad found for device sky130_fd_pr__pfet_01v8_lvt No property ps found for device sky130_fd_pr__pfet_01v8_lvt No property pd found for device sky130_fd_pr__pfet_01v8_lvt Model sky130_fd_pr__pfet_01v8_lvt pin 1 == 3 No property mult found for device sky130_fd_pr__pfet_01v8_lvt No property sa found for device sky130_fd_pr__pfet_01v8_lvt No property sb found for device sky130_fd_pr__pfet_01v8_lvt No property sd found for device sky130_fd_pr__pfet_01v8_lvt No property nf found for device sky130_fd_pr__pfet_01v8_lvt No property nrd found for device sky130_fd_pr__pfet_01v8_lvt No property nrs found for device sky130_fd_pr__pfet_01v8_lvt No property area found for device sky130_fd_pr__pfet_01v8_lvt No property perim found for device sky130_fd_pr__pfet_01v8_lvt No property topography found for device sky130_fd_pr__pfet_01v8_lvt No such pin 1 in model sky130_fd_pr__pfet_01v8_lvt Unable to permute model sky130_fd_pr__pfet_01v8_lvt pins 1, 3. No property as found for device sky130_fd_pr__pfet_01v8_lvt No property ad found for device sky130_fd_pr__pfet_01v8_lvt No property ps found for device sky130_fd_pr__pfet_01v8_lvt No property pd found for device sky130_fd_pr__pfet_01v8_lvt No property mult found for device sky130_fd_pr__pfet_01v8_lvt No property sa found for device sky130_fd_pr__pfet_01v8_lvt No property sb found for device sky130_fd_pr__pfet_01v8_lvt No property sd found for device sky130_fd_pr__pfet_01v8_lvt No property nrd found for device sky130_fd_pr__pfet_01v8_lvt No property nrs found for device sky130_fd_pr__pfet_01v8_lvt No property area found for device sky130_fd_pr__pfet_01v8_lvt No property perim found for device sky130_fd_pr__pfet_01v8_lvt No property topography found for device sky130_fd_pr__pfet_01v8_lvt Comparison output logged to file comp.out Logging to file "comp.out" enabled Contents of circuit 1: Circuit: 'PMOS2.spice' Circuit PMOS2.spice contains 0 device instances. Circuit contains 0 nets. Contents of circuit 2: Circuit: 'pmos_tb.spice' Circuit pmos_tb.spice contains 0 device instances. Circuit contains 0 nets. Circuit PMOS2.spice contains no devices. Final result: Verify: cell pmos_tb.spice has no elements and/or nodes. Not checked. Logging to file "comp.out" disabled LVS Done.
m
You’re not using the command I suggested.
Copy code
netgen -batch lvs "PMOS2.spice PMOS2" "pmos_tb.spice pmos_tb" /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
m
and here's what i get when i type the command you suggested: netgen -batch lvs "PMOS2.spice pmos_tb" "pmos_tb.spice PMOS2" /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl Netgen 1.5.242 compiled on Sun Dec 11 233933 EET 2022 Warning: netgen command 'format' use fully-qualified name ':netgen:format' Warning: netgen command 'global' use fully-qualified name ':netgen:global' Reading netlist file PMOS2.spice Call to undefined subcircuit sky130_fd_pr__pfet_01v8_lvt Creating placeholder cell definition. Reading netlist file pmos_tb.spice Cannot find cell pmos_tb in file PMOS2.spice
m
pmos_tb.spice PMOS2
should be
pmos_tb.spice pmos_tb
PMOS2.spice pmos_tb
should be
PMOS2.spice PMOS2
m
here's what i got now: netgen -batch lvs "PMOS2.spice PMOS2" "pmos_tb.spice pmos_tb" /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl Netgen 1.5.242 compiled on Sun Dec 11 233933 EET 2022 Warning: netgen command 'format' use fully-qualified name ':netgen:format' Warning: netgen command 'global' use fully-qualified name ':netgen:global' Reading netlist file PMOS2.spice Call to undefined subcircuit sky130_fd_pr__pfet_01v8_lvt Creating placeholder cell definition. Reading netlist file pmos_tb.spice Reading setup file /openpdk/share/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl No property as found for device sky130_fd_pr__pfet_01v8_lvt No property ad found for device sky130_fd_pr__pfet_01v8_lvt No property ps found for device sky130_fd_pr__pfet_01v8_lvt No property pd found for device sky130_fd_pr__pfet_01v8_lvt Model sky130_fd_pr__pfet_01v8_lvt pin 1 == 3 No property mult found for device sky130_fd_pr__pfet_01v8_lvt No property sa found for device sky130_fd_pr__pfet_01v8_lvt No property sb found for device sky130_fd_pr__pfet_01v8_lvt No property sd found for device sky130_fd_pr__pfet_01v8_lvt No property nf found for device sky130_fd_pr__pfet_01v8_lvt No property nrd found for device sky130_fd_pr__pfet_01v8_lvt No property nrs found for device sky130_fd_pr__pfet_01v8_lvt No property area found for device sky130_fd_pr__pfet_01v8_lvt No property perim found for device sky130_fd_pr__pfet_01v8_lvt No property topography found for device sky130_fd_pr__pfet_01v8_lvt No such pin 1 in model sky130_fd_pr__pfet_01v8_lvt Unable to permute model sky130_fd_pr__pfet_01v8_lvt pins 1, 3. No property as found for device sky130_fd_pr__pfet_01v8_lvt No property ad found for device sky130_fd_pr__pfet_01v8_lvt No property ps found for device sky130_fd_pr__pfet_01v8_lvt No property pd found for device sky130_fd_pr__pfet_01v8_lvt No property mult found for device sky130_fd_pr__pfet_01v8_lvt No property sa found for device sky130_fd_pr__pfet_01v8_lvt No property sb found for device sky130_fd_pr__pfet_01v8_lvt No property sd found for device sky130_fd_pr__pfet_01v8_lvt No property nrd found for device sky130_fd_pr__pfet_01v8_lvt No property nrs found for device sky130_fd_pr__pfet_01v8_lvt No property area found for device sky130_fd_pr__pfet_01v8_lvt No property perim found for device sky130_fd_pr__pfet_01v8_lvt No property topography found for device sky130_fd_pr__pfet_01v8_lvt Comparison output logged to file comp.out Logging to file "comp.out" enabled Contents of circuit 1: Circuit: 'sky130_fd_pr__pfet_01v8_lvt' Circuit sky130_fd_pr__pfet_01v8_lvt contains 0 device instances. Circuit contains 0 nets. Contents of circuit 2: Circuit: 'sky130_fd_pr__pfet_01v8_lvt' Circuit sky130_fd_pr__pfet_01v8_lvt contains 0 device instances. Circuit contains 0 nets, and 4 disconnected pins. Circuit sky130_fd_pr__pfet_01v8_lvt contains no devices. Contents of circuit 1: Circuit: 'PMOS2' Circuit PMOS2 contains 96 device instances. Class: sky130_fd_pr__pfet_01v8_lvt instances: 96 Circuit contains 386 nets. Contents of circuit 2: Circuit: 'pmos_tb' Circuit pmos_tb contains 1 device instances. Class: sky130_fd_pr__pfet_01v8_lvt instances: 1 Circuit contains 6 nets. Circuit was modified by parallel/series device merging. New circuit summary: Contents of circuit 1: Circuit: 'PMOS2' Circuit PMOS2 contains 1 device instances. Class: sky130_fd_pr__pfet_01v8_lvt instances: 1 Circuit contains 386 nets. Contents of circuit 2: Circuit: 'pmos_tb' Circuit pmos_tb contains 1 device instances. Class: sky130_fd_pr__pfet_01v8_lvt instances: 1 Circuit contains 6 nets. Circuit 1 contains 1 devices, Circuit 2 contains 1 devices. Circuit 1 contains 6 nets, Circuit 2 contains 6 nets. Final result: Netlists do not match. Logging to file "comp.out" disabled LVS Done.
how do i know why they're not matched?
m
Progress! Take a look at
comp.out
m
Perfect, thanks so much!
@Mitch Bailey after many hours of debugging, i found out that the reason they didn’t match is that xschem extracts the device for example called “M0” but Magic extracts it “X0” and once i edited the netlists and made them both M0 , LVS matched, any idea how i can fix this issue in Magic?
m
Before creating the netlists from xschem, be sure to check
Simulation->LVS netlist: Top level is a .subckt
Also the mos devices should have the
spiceprefix=X
property.
m
oh great thanks for the info