#1515 unable to resolve hold timing on a simple design Issue created by mattvenn Description This is from a Tiny Tapeout design: https://wokwi.com/projects/341571228858843732 The verilog is fetched from: https://wokwi.com/api/projects/341571228858843732/verilog The flow fails at CTS. It might be because there are 2 outputs that are driven directly by the clock? Also, I am unable to resolve the PDK mismatch, even with a completely fresh install I get this. Expected Behavior Not fail CTS. Environment report

Kernel: Linux v5.15.0-53-generic
Distribution: ubuntu 20.04
Python: v3.8.10 (OK)
Container Engine: docker v20.10.7 (OK)
OpenLane Git Version: cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988
pip: INSTALLED
python-venv: INSTALLED
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PDK Version Verification Status: MISMATCH
The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c)
This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.
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Git Log (Last 3 Commits)

cb59d1f 2022-11-18T18:42:38+02:00 fix return values in `equally_spaced_sequence` (#1503) - Kareem Farid -  (grafted, HEAD, tag: 2022.11.19)
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Git Remotes

origin  <https://github.com/The-OpenROAD-Project/OpenLane> (fetch)
origin  <https://github.com/The-OpenROAD-Project/OpenLane> (push)

Reproduction material issue.tar.gz Relevant log output

[INFO RSZ-0046] Found 1 endpoints with hold violations.
[WARNING RSZ-0064] Unable to repair all hold checks within margin.
[INFO RSZ-0032] Inserted 254 hold buffers.
[ERROR RSZ-0060] Max buffer count reached.
Error: resizer_timing.tcl, 48 RSZ-0060
child process exited abnormally

The-OpenROAD-Project/OpenLane