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m

Matt Liberty

05/08/2023, 6:31 PM
Does anybody know what happened to the docs at https://antmicro-skywater-pdk-docs.readthedocs.io/ ? I get a 404 now.
a

Andrew Wright

05/08/2023, 7:10 PM
I noticed the same thing on the weekend also when looking up the GPIO datasheets.
m

Mitch Bailey

05/08/2023, 9:33 PM
@Matt Liberty @Andrew Wright Does https://skywater-pdk.readthedocs.io/en/main/ have what you want? I think the
antmicro
version was “unofficial”.
m

Matt Liberty

05/08/2023, 9:38 PM
Where would I find the description of a std cell, eg sky130_fd_sc_hd__dfsbp_1 ?
m

Mitch Bailey

05/08/2023, 10:10 PM
It’s probably not in a very usable format, but what about here?
m

Matt Liberty

05/08/2023, 10:41 PM
The ant micro version was much nicer without having to dig through the details
😂 1
d

dlmiles

05/08/2023, 11:59 PM
I am attempting to produce an improved online version, but I am having to learn quite a bit of VLSI theory at the same time. So if anyone has some math to compute 'Dynamic Power', 'Intrinsic Delay' and 'Delay Kload' ideally directly from liberty (.lib) file data, if not possible then with SPICE model snippets, I can probably close out stage 1 on this.

https://user-images.githubusercontent.com/293087/235223230-05a3f3b4-1ddd-4b4e-ab1c-1baf6cdfd784.png

DRAFT outline of the concept, please DM.
👍 1
m

Mitch Bailey

05/09/2023, 12:20 AM
Nice work @dlmiles! Currently the spice file associated with each cell is an extracted netlist generated from the layout. The corresponding cdl file appears to be generated from a schematic editor, but the original data is unavailable as far as I know. It might be helpful to have a xschem schematic with test inputs for each cell. In the variations section under artifacts, what does NETLIST represent?
In another iteration of the concept this kind of data can be annotated to the CMOS Circuit section. Can you point me to a file that would be an example of the 'xschem schematic with test inputs' ? so I can keep for reference to look at transforming/converting data into that format. Does this help with the 3 main data points 'Dynamic Power', 'Intrinsic Delay' and 'Delay Kload' those are the immediate hurdles.
m

Mitch Bailey

05/09/2023, 2:20 AM
There’s test bench for a relatively simple circuit in
caravel/xschem/simple_por_tb.sch
. This is what a xschem schematic file would look like for an inverter (sizes and models may differ)
v {xschem version=3.0.0 file_version=1.2 }
G {}
K {}
V {}
S {}
E {}
N -40 -30 -40 30 {
lab=A}
N -120 -0 -40 0 {
lab=A}
N 0 0 100 -0 {
lab=Y}
C {sky130_fd_pr/nfet3_01v8.sym} 620 260 0 0 {name=M1
L=0.15
W=1
body=GND
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'" 
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'" 
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=nfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/pfet_01v8.sym} -20 -30 0 0 {name=M2
L=0.15
W=1
nf=1
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'" 
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'" 
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=pfet_01v8
spiceprefix=X
}
C {sky130_fd_pr/nfet_01v8.sym} -20 30 0 0 {name=M3
L=0.15
W=1
nf=1 
mult=1
ad="'int((nf+1)/2) * W/nf * 0.29'" 
pd="'2*int((nf+1)/2) * (W/nf + 0.29)'"
as="'int((nf+2)/2) * W/nf * 0.29'" 
ps="'2*int((nf+2)/2) * (W/nf + 0.29)'"
nrd="'0.29 / W'" nrs="'0.29 / W'"
sa=0 sb=0 sd=0
model=nfet_01v8
spiceprefix=X
}
C {devices/gnd.sym} 0 60 0 0 {name=l1 lab=GND}
C {devices/vdd.sym} 1280 460 0 0 {name=l2 lab=VDD}
C {devices/opin.sym} 620 260 0 0 {name=p1 lab=xxx}
C {devices/ipin.sym} -120 0 0 0 {name=p2 lab=A}
C {devices/opin.sym} 100 0 0 0 {name=p3 lab=Y}
C {devices/vdd.sym} 0 -60 0 0 {name=l3 lab=VDD}
This is how the corresponding visual representation of the schematic would appear (bulk connections added).
h

htamas

05/09/2023, 3:26 PM
@Matt Liberty I guess it was taken down because it's 2.5 years out of date but still comes up as the top result on google. The main branch of antmicro's fork is just an old version of the official one, but they had a nice side branch called "test-submodules-in-rtd" that contained the cell info, schematics & layout.
m

Matt Liberty

05/09/2023, 3:26 PM
I've asked antmicro if they have scripts or other things that we could reuse
h

htamas

05/09/2023, 3:27 PM
You should check out the "test-submodules-in-rtd" branch.
Or ideally take the changes in that branch and merge it on top of the official one (https://github.com/google/skywater-pdk)
I've mostly done it in my fork (https://github.com/htfab/skywater-pdk), but it still needs some work to compile cleanly.
Ok, I've managed to build the docs. As a stopgap measure, you can find the cell information at https://htfab.github.io/skywater-pdk/contents/libraries.html#foundry-provided-digital-standard-cell-libraries I don't intend to keep it up to date, so let's get it merged back upstream.
m

Matt Liberty

05/10/2023, 5:52 PM
The PRs related to this have been merged and the docs are much nicer, eg https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_ls/cells/a2111o/README.html
👍 2
d

dlmiles

05/10/2023, 10:45 PM
Good to see PRs getting merged to prevent project apathy. Is the main catalog of cells up there ? https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/README.html I think this would be the expected location for HD. Ah I see you have posted cell-index.html (good for seeing type matrix) but it doesn't have the nice one sentence cell function summary for quick reference, as most of my usage has been within a single type (HD) and then looking up the relative function by summary description.
h

htamas

05/10/2023, 11:59 PM
Looks like antmicro's version included some changes that were not in PR#266. Compare https://skywater-pdk.readthedocs.io/en/main/contents/libraries/sky130_fd_sc_hd/README.html to https://htfab.github.io/skywater-pdk/contents/libraries/sky130_fd_sc_hd/README.html . Is there another relevant PR or should we manually copy cell_list.py to the official repo and include it in docs/conf.py?