Hi, I need help validation of timing tables of various std lib cells, utilising SPICE simulations. The goal would be to crate a general-purpose timing model for STA. Any help, guidance or reference?

You are basically trying to replicate these tools: https://www.cadence.com/en_US/home/tools/custom-ic-analog-rf-design/library-characterization/liberate-trio-characterization-suite.html https://www.synopsys.com/implementation-and-signoff/signoff/siliconsmart.html

But in open source, therefore, I need a starting point, like the SPICE models and script used to create open source Sky130A timing data.

If your concern is the validity of the std cells. The technology has shipped a few billion (with a B) units. The spice models are available in the PDK. The scripts are not and will never be. The STD cell characterization just runs each gate inside a defined testbench. The testbench has defined/specified drive and load.

@Andrew Wright As I mentioned, we are trying to accelerate and improve STA and a good starting point is to replace table lookup and interpolation with generalized models. To train such model, I want SPICE models of standard cell and those test benches, which were deployed to generate Liberty LUTs of Sky130A pdk.