Pretty basic question: I have a hold timing violation and it is mostly due to the fact that the input is a primary input with an ideal clock and the output is a DFF with a clock from the clock tree. What is the recommended way to resolve such an issue?

set_input_delay?

@Kunal Yes, I suppose it would be right, but it would need to be set comparable to the clock insertion delay.

You can indeed play with the input delay or the clock latency on your virtual clock. But in general, you can kind of ignore hold violations on IOs in the first order as most of them would not really happen when you integrate with a parent module. Especially if you don't have a good idea (yet) of delays outside of your block. Running flat STA later would be the correct check. (in the case of having a hierarchical implementation, not sure this is your case)

Either you can set false path in IO for hold OR set_clock_latency for the virtual clocks with median number.

I think the best solution in this case is to split the input and output delays. Right now they are 20% for both input and output. Setting it to 50% worked better in this case, but it also may make sense to have different values.