<@U016EM8L91B> Is there a way to do a gate level s...
# mpw-2-silicon
k
@Tim Edwards Is there a way to do a gate level sim with sky130 in Icarus with sdf annotation? It looks like the stdcells verilog I have is not annotated with timing information, so I see this error: “Omitting $sdf_annotate() since specify blocks are being omitted”. Is there another verilog file available with the specify blocks? Thanks!
l
I think this is because specify was not enabled via the command line flags in iverilog Please see "specify/no-specify": https://steveicarus.github.io/iverilog/usage/command_line_flags.html Unfortunately, you will still be out of luck as sdf support in Icarus Verilog is limited: https://github.com/steveicarus/iverilog/issues/746
t
@Leo Moser: I was going to say that CVC is not open source and there were license restrictions that prevented us from integrating it with other tools ourselves. But the only version I knew about came directly from Tachyon, and you posted a github link I wasn't aware of. Where did this open source version come from?
l
The source of the simulator was released by Tachyon as OSS CVC: http://www.tachyon-da.com/ The cambridgehackers uploaded the source to GitHub to fix various issues, but the actual source code has not been updated in ~7 years. The code is licensed under a Perl style artistic open source license: http://www.tachyon-da.com/wp-content/uploads/2016/04/OSS-CVC-MODIFIED-ARTISTIC-LIC.txt I'm no expert on these things, but I think that for minor changes Tachyon retains the copyright and thus can include the changes into their proprietary version. That might have prevented you from integrating it with other tools? This FAQ tries to explain it: http://www.tachyon-da.com/wp-content/uploads/2014/12/OSS-CVC-ARTISTIC-LICENSING-FAQ.pdf