Hello, I am running LVS on my circuit design that uses standard cells. However, I am getting some odd net mismatches. Each output pin (labeled Q#) is connected in an identical manner to a the output of a NAND gate, and is then fed into the input of an inverter. These instances are essentially copies of each other, aside from the NAND inputs (which are not causing an issue). For some reason, some of the output nets are matching properly, and some are not. I have attached some snapshots of the netgen output (left side is from schematic, right side is layout). Also, I've included some pictures from magic to show that the output connections are configured in the same manner (QN1 is fine, QN2 is not). I threw in a picture of the schematic, but I don't think it will help much since they are standard cells. Any help is appreciated -- thanks!

@David Bertuch Remember that with netgen, pin order to logic gates is relevant. A + B -> Z will not match B + A -> Z.

Hi, thanks for the response. It seems my select lines have no problem matching up. The only issue is the output net of the NAND gate. I am almost certain that my select signals match the schematic (in the correct order). It just seems odd that two outputs, wired in an identical manner, have a different ordering of nfets and pfets in netgen -- is this independent of inputs?

Can you post your extracted netlist, verilog and/or spice source netlist, the command that you use to execute netgen with all the parameters, and the full output log?