Hi <@U016EM8L91B> <@U017X0NM2E7> Excuse me, can yo...
# lvs
a
Hi @Tim Edwards @Mitch Bailey Excuse me, can you guide me to know how to fix this lvs , please? Note: 1-The extracted spice file is simulated successfully. 2-Get spice file from MAGIC using
gds read <cell>
flatten -doinplace dac_3v_8bit
extract do local
extract all
ext2spice lvs
ext2spice
Thanks.
t
@Ahmed Reda: Looks like a pin ordering issue on the schematic side:
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---------------------------------------------------------------------------------------
Net: eoc                                   |Net: eoc
  sar/eoc = 1                              |  sar/eoc = 1
                                           |
Net: soc                                   |Net: soc
  sar/soc = 1                              |  sar/dvss = 1
                                           |
Net: rst_n                                 |Net: rst_n
  sar/rst_n = 1                            |  sar/dvdd = 1
                                           |
Net: clk                                   |Net: clk
  sar/clk = 1                              |  sar/data[7] = 1
---------------------------------------------------------------------------------------
You've got "clk" connected to "data[7]", "rst_n" tied to "dvdd", etc.
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.subckt sar clk cmp data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] dvdd dvss eoc hold rst_n soc
in
sar.spice
vs.
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X4 data[0] data[1] data[2] data[3] data[4] data[5] data[6] data[7] cmp clk rst_n soc eoc hold dvdd dvss sar
in
SAR_ADCx.spice
.
a
@Tim Edwards Thanks Is there way to adjust the pin ordering issue on the following schematic? should i do it manually? or it is an issue during connecting the schematic!
t
@Ahmed Reda: I think it has more to do with the contents of
sar.sym
. You're connecting to an external netlist named
sar.spice
and xschem needs to know how to output the connections in the same order as the pins are defined in that file, without knowing anything about that file.
1
a
Thanks @Tim Edwards . I got it.
m
@Ahmed Reda Looks like you’re trying to combine an extracted netlist with a schematic generated netlist. As Tim said you need to make sure the pins are in the correct order. I believe you can do a
read spice
in magic before extraction to extract the ports in the same order. See here. You also have a resistance model mismatch in
follower_amp
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Circuit 1: follower_amp                    |Circuit 2: follower_amp                    
-------------------------------------------|-------------------------------------------
sky130_fd_pr__pfet_g5v0d10v5 (415->10)     |sky130_fd_pr__pfet_g5v0d10v5 (10)          
sky130_fd_pr__nfet_g5v0d10v5 (132->10)     |sky130_fd_pr__nfet_g5v0d10v5 (10)          
sky130_fd_pr__res_xhigh_po (4->1)          |(no matching element)                      
sky130_fd_pr__nfet_03v3_nvt (2)            |sky130_fd_pr__nfet_03v3_nvt (2)            
sky130_fd_pr__diode_pw2nd_05v5 (2)         |sky130_fd_pr__diode_pw2nd_05v5 (2)         
(no matching element)                      |sky130_fd_pr__res_xhigh_po_0p35 (1)
magic cannot extract
sky130_fd_pr__res_xhigh_po_0p35
from gds so you’ll have to manually change the source netlist from
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XR1 net4 vdd vss sky130_fd_pr__res_xhigh_po_0p35 W=1 L=100 mult=1 m=1
to
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XR1 net4 vdd vss sky130_fd_pr__res_xhigh_po W=0.35 L=100 mult=1 m=1