Hello everyone! Please I'd like to make a request. I'm an undergraduate currently in my senior year. I recently learnt about amplifier design using the gm/Id method. Yes, I understand the motivation and merit of the gm/Id method. However, I'd still like to get a feel of the practical use of it in amplifier design. I'd like a step by step walk through of a single stage op amp design using the gm/Id approach. I'd like to see how the method can be used to design a differential amplifier with active load and biasing (current mirrors) from specifications to hand calculation(I'm aware look-up tables/charts would be utilised) design using the 180nm technology. After I must have learned from the practical walk through, I'd then design my own opamp with different specifications using the method and I'd simulate it on SPICE for verification. I'd be glad to practically apply this method myself. Coming from the sqaure-law background there is really a lot of information in the gm/Id approach. I've studied some papers and lecture notes and I've grasp the motivation of the method but I want to use it practically in amplifier design. Thank you for your consideration.

@Emmanuel Innocent I am unaware of a walk-through example applying gm/Id, unfortunately, but you can look into Behzad Razavi’s column “The Analog Mind” in the IEEE Solid-State Circuits Magazine. There he features examples of how he develops circuits step-by-step which is quite insightful because you can follow the line of thinking of a master circuit designer. Apart from that, maybe you find examples to follow in Willy Sansen’s book “Analog Design Essentials.” Apart from that, gm/Id is not too complicated; it is just a very handy tool to properly size a MOSFET once you leave the Vod>150mV land (aka strong inversion), and work with Vgs ~ Vth (medium inversion) or below (weak inversion). Similar to the gm/Id method is the use of the inversion coefficient (IC), which is quite similar and well described in various papers.

Try the simple example starting on slide 24 of this pdf:

First of all, you need an application for your amplifier. If you don't have any specifications, there is no reason to use gm/id or anything else. For example, if you want to design an amplifier for a given GBW, you can define the differential pair transconductance (gm). But you also need to define your amplifier maximum load, if it will be purely capacitive, or resistive. For a given load, and power specifications, slew rate, anything, you will set the currents it use.

Thank you very much @Luis Henrique Rodovalho and @Harald Pretl for the insights. Professor @Boris Murmann thank you very much for the slides, the gm/Id based design concept was broken down in simple language. The simple design example was also helpful. I now understand the approach's motivation more. However, please I have a question: After sizing, how do I bias the transistor(s)? After applying the gm/Id approach, I now have information about the currents through each transistors, say, in a single stage opamp. But how do I determine the voltages if for instance I want to determine the value of the resistors to be used for biasing(or as passive loads) in the amplifier circuit? This difficulty keeps forcing me to use the Vgs, Vds, and Vtn relationship e.g Vds >= Vgs - Vtn. PS: I did not fully understand what this means, from slide 25 of the pdf:

"Note: Numbers have some VDS dependence, but this typically gives errors of less than 10%. A good guess for VDS is OK."

I think these statements may be a pointer to the biasing question I asked. Thank you very much sir.

This is really where all the "conventional" textbook material comes in (nothing to do with gm/ID). You pick a circuit topology that is robust, which usually implies that the circuit is current biased. In other words, you have number of current sources and mirrors in the circuit, and the topology is constructed such that all the VGS and VDS "compute themselves." Given the large Vt variations in CMOS, you usually cannot voltage bias the circuits. You can read the biasing chapter in my intro book: https://github.com/bmurmann/Book-on-MOS-stages

Wow, interesting! Things are getting clearer! First, Professor, thank you for this book and other books I received from you. This book has really been helpful. I've been on this book for a while now. I'm presently in the section before that which you discussed self-biasing circuit configuration with current mirrors. So, it's time to go continue studying the book so I can have my question answered! Thank you.

First of all, you will have an non ideal current source. Most times, it is a PTAT current source (the reference current increases with temperature). Your differential pair should have a gm that is somehow independent of temperature. This way you can find the gm/id of your pair. The other transistors in the design of most amplifiers aren't as important. Maybe the second voltage gain stage. But it is extremely important that all transistors have similar total active areas, so they will have approximately the same mismatch and flicker noise contributions. If all transistors have the same gm/id, they will probably have the same tolerance to mismatch and output noise.