#1776 synthesis.tcl: run_verilator --lint-only option changes Pull request opened by dlmiles Rationale --no-timing make it not error on timing statements: assign #1 out = !in; +define+SYNTHESIS=1 as this pass is on behalf of the synthesis phase so should not include verilog which is not for synthesis. Such as blackboxed primitives. +define+SYNTHESIS_VERILATOR_LINT_ONLY=1 like the above but provide more explicit control over this specific OpenROAD task to ignore. Maybe this option should be added to documentation ? The-OpenROAD-Project/OpenLane