has anyone checked the DLL ? to get faster internal clocks?

I have run the DLL. Except that up to the MPW-5 redesign, the DLL itself doesn't work in locked mode because the bit in the SPI that enables it can't be set. But I have been able to turn it on in DCO mode (digital-controlled oscillator; that is, free-running with the trim controlled directly from the trim bits in the SPI register and/or memory map) and run up to 40MHz or close to it, which is the point at which the processor fails. There are bits that can't be set in the divider values, too, so there are somewhat limited choices of clock speed, but it does work.

if I wanted an internal wb_clk of 300M (not caring if the processor fails) - is that possible from now onwards?

No, this DCO is not designed to hit 300MHz. I think I targeted 150MHz and ended up with something a bit lower, like 120.

ok

@Matt Venn: That script is just indicating what the feed-forward and feed-back dividers need to be to lock the oscillator to a specific input frequency. It's all math, though, and doesn't account for the fact that the DCO will not actually hit all those numbers.

My code is just theoretical

ok

The code, or the DLL?

the DLL

I tested the DCO part of the DLL (everything but the feedback mechanism). Testing the actual DLL will have to wait for MPW-6 (I think?), which is I think the first tapeout where the hold issues inherent in the housekeeping block (because the synthesis setup did not treat the SPI SCK line as a clock) were fixed.

ok