We have a core of only macros on our User_project_wrapper top-level. In order to try and resolve the slew warnings for our top level clock signals that have high fanouts we wanted to turn on clock tree synthesis. When attempting to do this we get LVS errors that show the new cells added to the top level are not connected to power. The LVS errors also show up whenever we try to run any configuration that seems to add cells to the top level ie. diode insertion, buffer insertion, design optimization. We do have synth_elaborate_only on, but assumed that would only affect the synthesis step of the flow. Does this behavior make sense at all?

@Taylor P the power in macros needs to be connected with

FP_PDN_MACRO_HOOKS

. See https://openlane.readthedocs.io/en/latest/reference/configuration.html and read the warning.

correct, we already have power connections for the macros. But when we run clock tree synthesis in user project wrapper to fix the slew of our clock network, the clock tree that is generated the cells that are part of it, seem to be unconnected to power.

If you're enabling CTS, new buffers will be added. Those need power rails connection, tap/decap insertion. Just check following is enable or disabled?

set ::env(FP_PDN_ENABLE_RAILS) 0
set ::env(RUN_FILL_INSERTION) 0
set ::env(RUN_TAP_DECAP_INSERTION) 0
set ::env(CLOCK_TREE_SYNTH) 0

We had run_fill_insertion and fp_pdn_enable_rails off as we were trying to closely match the template config.json for user_project_wrapper, do all of the above settings need to be enabled?