#1768 [ERROR]: Mismatch during LVS Issue created by akhilesh911 Description Hello everyone, I am new to OpenLANE and trying to rebuild a 16 bit processor using caravel user project. The repo is given here. I am using gf180 PDK for this purpose. The design uses two macros, interface and processor, and four SRAM cells of gf180 PDK. There are mismatch in SRAM power pins, vdd and vss. But not such error in case of other macros. *Net: processor/vdd |(no matching net) processor/vdd = 1 | | Net: processor/vss |(no matching net) processor/vss = 1 |* * * * Net: vss |(no matching net) gf180mcu_fd_ip_sram__sram256x8m8wm1/VSS | | Net: vdd |(no matching net) gf180mcu_fd_ip_sram__sram256x8m8wm1/VDD | The log files are attached. 23-lvs.lef.log 23-user_project_wrapper.lef.lvs.log Expected Behavior No erros. Flow complete. Environment report

Kernel: Linux v5.4.0-146-generic
Distribution: ubuntu 18.04
Python: v3.6.9 (OK)
Container Engine: docker v20.10.17 (OK)
OpenLane Git Version: a35b64aa200c91e9eb7dde56db787d6b4c0ea12a
pip: INSTALLED
python-venv: INSTALLED
---

Reproduction material No reproducible issues found. Relevant log output

[INFO]: Writing Verilog (log: ../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/logs/signoff/21-write_powered_verilog.log)...
[INFO]: Running LVS (log: ../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/logs/signoff/23-lvs.lef.log)...
[ERROR]: There are LVS errors in the design: See '../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/reports/signoff/23-user_project_wrapper.lvs.rpt' for a summary and '../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/logs/signoff/23-lvs.lef.log' for details.
[INFO]: Saving current set of views in '../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/results/final'...
[INFO]: Generating final set of reports...
[INFO]: Created manufacturability report at '../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/reports/manufacturability.rpt'.
[INFO]: Created metrics report at '../home/signoff/16bit-pipelined-RISC-processor-gf180/openlane/user_project_wrapper/runs/23_04_18_14_44/reports/metrics.csv'.
[INFO]: Saving runtime environment...
[ERROR]: Flow failed.

The-OpenROAD-Project/OpenLane