Zeyi Wang
04/19/2023, 10:35 PMEric
04/20/2023, 12:32 AMStefan Schippers
04/20/2023, 8:30 AMStefan Schippers
04/20/2023, 8:35 AMHarald Pretl
04/20/2023, 8:42 AMyrrapt
04/21/2023, 4:34 PMHarald Pretl
04/21/2023, 4:36 PMEric Smith
04/23/2023, 6:07 PMyrrapt
04/23/2023, 7:18 PMtol_m3
in the spice models.
Assuming a connecting metal of width 1 um and 0.065 um offset there's a 0.065 um^2 area error. Assuming a comically small MiM cap of 2x2 um that's an error of 1.6%, that's obviously nothing compared to the cap area tolerance which is listed as 20% for sky130 MiM. Take a 20x20 um cap and it's a 0.02% error.
To me the change in absolute capacitance is completely dwarfed by the normal tolerance of the capacitor.
(note: fringe capacitance is not taken into account here)
The bigger question then is about mismatch between devices. I would guess that any mask misalignment would match between devices and this wouldn't have any (maybe too strong a word) improvement. But there may be some faulty assumptions there.