Bala Dhinesh04/18/2023, 9:55 AM
Thanks in advance!
Matthew Guthaus04/18/2023, 10:17 AM
Bala Dhinesh04/18/2023, 12:27 PM
Matthew Guthaus04/18/2023, 1:44 PM
Bala Dhinesh04/18/2023, 1:47 PM
is not there in caravel repo - https://github.com/efabless/caravel/tree/main/verilog/rtl
Matt Venn04/18/2023, 3:43 PM
Bala Dhinesh04/18/2023, 4:37 PM
command. This created a new directory called
. When I ran make of
example I get the following error. It seems that
file is missing. Did I miss anything? I'm quite new to OpenLane. Sorry if this is something very basic. Basically I want to do verification for a sample application and obtain the waveform.
Matt Venn04/19/2023, 7:41 AM