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Has anyone used the XSPICE extension of NGSPICE? I...
# analog-design
l
Has anyone used the XSPICE extension of NGSPICE? If so, how would you rate your experience with XSPICE?
s
I have tried it, using @Tim Edwards 
spi2xspice.py
script from qflow. By using the generic Xspice LUT and the DFF models all standard cells (combinatorial and sequential) can be simulated at digital level. In xschem_sky130 there is a 
sky130_tests/test_stdcells.sch
that does a side by side comparison of some digital logic, one block simulated at analog level, the other identical block simulated at XSPICE level. The outputs are the same. One thing that I do not like of LUT devices is that the output is undefined (X) if one of the inputs is undefined. This is not accurate for some logic functions. If a NAND gate has one input low and the other input undefined (X) the output is high (1) regardless of the undefined second input.
t
@Larry Harris: I wrote the LUT model that Stefan is referring to above so that I could convert any standard cell design into an xspice equivalent. I have found it very helpful; it lets me simulate circuits with the complexity of a microcontroller and it doesn't slow down the simulation to a crawl. Per Stefan's caveat above, it does have limitations, and it shouldn't be used to test the validity of the subcircuit. Its primary use is to make it feasible to simulate mixed-signal circuit that have a large digital component.
l
Stefan and Tim, Thank you for the information. My design is at the point where I am adding logic gates to control my analog sub-circuits. With the logic gates added, when I simulate at the transistor level, my simulations take a very long time to calculate a dc operating point. I assume it has to do with all the "series node connection" in my logic gates that can be floating if the logic is in the wrong state. As a test, I am going to add a 100Meg ohm resistor to ground on all the "series nodes" in my own logic gate library. I will let you know what kind of speed up the additional resistor has on my simulations.
Adding the 100Meg ohm resistors to ground on the "series connected nodes" did NOT speed up my Dc operating point analysis. I guess the slowness in my dc operating point analysis is due to the large number of nodes in my circuit design. It appears that I am going to have to learn how to use XSPICE.
t
@Larry Harris: You can try setting initial conditions. How much logic do you have? Small amounts of logic should simulate reasonably well with ngspice. Otherwise, yes, I'd go with xspice; the point of the spi2xspice.py script is it generates a subcircuit that can be swapped directly with the original in the netlist.
h
@Larry Harris We have used XSPICE for a full mixed-signal simulation of a 12b SAR-ADC, analog blocks using a PEX netlist plus Verilog control logic simulating in XSPICE. Here you go for inspiration: https://github.com/iic-jku/SKY130_SAR-ADC1
l
Tim and Harald thanks for the guidance. Presently, I am simulating a digitally calibrated low noise comparator. This is part of a PipeLine ADC that I am working on. All my digital logic is presently at the transistor level and I have been only using NGSPICE. When I added the state machine for the digital calibration engine, all my simulations slowed way down. I am now at the point where I need to transition to much faster simulator. If you think XSPICE is a good simulator, I will take the time to learn that CAD tool.
h
@Larry Harris it works. If you need a pro-solution maybe coupling Xyce with Verilator or iVerilog has better speed, but we have no experience with that.
l
I am also running into a memory allocation issue with my NGSPICE simulations running interactively inside XSCHEM. The attached screen shot is the memory usage message I am getting inside my simulation command window. I am running XSCHEM on my Linux workstation with the Ubuntu operating system. I am presently only using 12% of my workstation's memory. How do I allocate more memory to my NGSPICE simulations?
For more information on my XSCHEM setup, the following screenshot is a image of my my XSCHEM Simulation Configuration window
s
@Larry Harris In interactive mode ngspice keeps in memory the whole data file, it will be eventually written (if there is a write instruction) at the end. You can try: • Batch ngspice mode: the raw file is written to disk as simulation goes. You lose all .control/.endc constructs, so remove all interactive commands and do a plain .tran • reduce the number of saved variables (avoid .save all) explicitly save the nodes you are interested in.
h
@Stefan Schippers ah I didn’t know that difference between batch and interactive, thanks for sharing.
s
You can attach the 
devices/spice_probe.sym
symbol to nets you want to save. xschem will emit the relevant .save line in the netlist. Similarly if ypu put a 
devices/ammeter.sym
device in a branch the branch current will be saved. So you don't have to write complex ,save .... lines.
@Harald Pretl
h
@Stefan Schippers well, I really should check the ngspice manual more often 😉
l
Thank you Stefan, your help is very much appreciated.
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Hi Harald, Stefan, and Tim I am chasing down charge transfer errors in my NGSPICE switched-capacitor circuit simulations. I am using ideal OpAmps, modeled with voltage-controlled-voltage sources, which have an open-loop gain of 100dB. The only real devices I have in my circuit are Capacitors and Nmos switches. I don't know if the charge transfer errors that I am seeing in my simulations are real or due to inappropriately set simulation control options. What simulation accuracy control options do you recommend for switched-capacitor circuits. Presently, I have been using the following options: method=gear abstol=1e-12 vntol=1e-6 chgtol=1e-14 gmin=1e-14 trtol=1
h
I never designed precision switched-capacitor circuits (only medium precision, so charge conservation to a high degree was not one of my concerns) so I am walking on a limb here. 
gear
shows weak numerical damping, 
trap
has no damping, so you might try that. In addition, BSIM are poor models for precision analog, PSP would be better, but this is beyond your control. Also, make sure that the 
GMIN
parameter is set low enough so that unwanted leakage currents do not affect your simulation.
One way to find out if settings are appropiate (I read this once somewhere): Do repeated simulations and keep tightening the parameters. Once you see no impact on the results any longer you know that the parameter is set tight enough.
l
Thanks Harald, I appreciate your feedback. To give you a little information about myself. I retired a couple of years ago after a 42 year carrier designing precision analog / mixed signal circuits. After sitting around for about a year, I got bored enough to start designing circuits again. I really do appreciate SkyWater Technologies and Efabless. They have enabled me to keep doing what I love. More importantly, I can do what I love on my own schedule.
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h
Great, that is the beauty of open-source IC design, anyone can do it just for fun, no license cost/NDA, and get it fabricated for relatively little money. You might also be interested in this, continuous delivery of the different pieces of this PDK over the next 1-2 years. This process (especially the SiGe NPNs) are great. https://github.com/IHP-GmbH/IHP-Open-PDK
@Larry Harris If you ever share/open-source your design at some point, please give me a ping. I am strongly interested in all things analog/mixed-signal/RF.
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